Fast and efficient circuit for identifying errors introduced in Reed-Solomon codewords

ABSTRACT

Apparatus and methods are disclosed for providing an improved system for identifying the location and value of errors introduced in binary data encoded using Reed-Solomon and related codes and to detect miscorrections of such codes with an auxiliary code. The invention employs an architecture based on a microcode engine that is specialized for error identification and that supports interleaved codewords. This architecture can be efficiently fabricated as an integrated circuit, yet is capable of identifying multiple introduced errors &#34;on the fly&#34; i.e. with performance sufficient to not significantly slow the process of reading from data storage or transmission subsystems such as, but not limited to, optical disks. In the preferred embodiment, a new two-step method of error syndrome computation is employed to reduce circuit cost and complexity. An improved iterative algorithm is provided which reduces circuit cost and complexity and decreases the time required to generate the error locator polynomial. Cyclic redundancy check (CRC) information is adjusted as introduced errors are identified during the Chien search, thus reducing the time required to protect against ECC miscorrection. Externally-specified error thresholds allow detection of excessive numbers of errors.

BACKGROUND OF THE INVENTION

This invention relates to information storage and retrieval ortransmission systems, and more particularly to means for encoding anddecoding codewords for use in error detection, identification andcorrection in such information systems.

Digital information storage devices, such as magnetic disk, magnetictape or optical disk, store information in the form of binary bits.Also, information transmitted between two digital devices, such ascomputers, is transmitted in the form of binary bits. During transfer ofdata between devices, or during transfer between the storage media andthe control portions of a device, errors are sometimes introduced sothat the information received is a corrupted version of the informationsent. Errors can also be introduced by defects in a magnetic or opticalstorage medium. These errors must almost always be corrected if thestorage or transmission device is to be useful.

Correction of the received information is accomplished by (1) derivingadditional bits, called redundancy, by processing the originalinformation mathematically; (2) appending the redundancy to the originalinformation during the storage or transmission process; and (3)processing the received information and redundancy mathematically todetect, identify and correct erroneous bits at the time the informationis retrieved. The process of deriving the redundancy is called encoding.The process of processing the received information and redundancy iscalled decoding. One class of codes often used in these processes isReed-Solomon codes.

Encoding of information is accomplished by processing a sequence ofinformation bits, called an information polynomial or information word,to devise a sequence of redundancy bits, called a redundancy polynomialor word, in accord with an encoding rule such as Reed-Solomon codes. Anencoder processes the information polynomial with the encoding rule tocreate the redundancy polynomial and then appends it to the informationpolynomial to form a codeword polynomial which is transmitted over thesignal channel or stored in an information storage device. When acodeword polynomial is received from the signal channel or read from thestorage device, a decoder processes the received codeword polynomial todetect the presence of error(s), to attempt to identify any error(s)present and to flag the information polynomial as erroneous or tocorrect it before transferring the information polynomial for furtherprocessing.

The decoding process typically comprises three steps: (1) computingfrequency-domain syndromes from the received codeword; (2) computing anerror locator polynomial, whose roots indicate the locations oferroneous symbols, from the frequency-domain syndromes; and (3) findingthe roots of the error locator polynomial and computing thecorresponding error values.

SECTOR FORMATS

The length n of codewords of Reed-Solomon codes utilizing b-bit symbolsis restricted to n<2^(b). A symbol size commonly used is the "byte"comprising eight bits, giving n<2⁸ =256. When it is desired to store inand retrieve from a data storage system, or send and receive over asignal channel, a group of more than 255 bytes together, more than onecodeword is required. When errors tend to occur in bursts affecting morethan one symbol, it is advantageous to interleave the codewords so thata single error burst is spread across more than one codeword.

Optical disks conforming to ANSI/ISO standards for 90 mm and 130 mmmedia store data in a sector comprising an identifying mark; atriply-redundant header containing physical location information; 512 or1024 user-data bytes plus vendor-unique/pointer bytes, all protected byan overlay CRC code with four redundant bytes, in five or teninterleaved ECC codewords, respectively, each with sixteen redundantbytes; and other necessary special marks. See 90 mm Rewritable/Read OnlyOptical Disk Cartridges for Information Interchange, Second Edition,Second Draft, JTC 1/SC 23/WG 2 N213, December 1990, pages 38-42 and84-86. Also see Information Technology--130 MM Rewritable Optical DiskCartridges for Information Exchange, ISO/IEC JTC 1/SC 23N, pages 53-57.FIG. 1 shows the organization of a 512-user-date-byte sector for theANSI 90 mm rewritable optical disk standard. FIG. 2 shows theinterleaved codeword organization of the data area within each 512-databyte sector for the ANSI 90 mm CCS rewritable optical disk standard. The"SB" and "RS" bytes are not included in ECC/CRC computations.

SYNDROME COMPUTATION

A Reed-Solomon code with distance d over b-bit symbols from GF(2^(b))has code generator polynomial G(x) of degree d-1: ##EQU1## where m isthe offset of the code generator polynomial. ⊕ represents finite-fieldaddition and the product is formed using finite-field multiplication.The time-domain remainder polynomial R(x) has coefficients R_(j) for jfrom 0 to d-2 defined by ##EQU2## where C'(x) is the received codewordpolynomial and the summation is performed using finite-field addition.Frequency-domain syndromes S_(m+i) for i from 0 to d-2 are related tocoefficients R_(j) according to: ##EQU3##

Rearranging equation (3) yields: ##EQU4##

Methods for performing the computations of equation (4) when m is zeroare known in the art; see Lim, "A Decoding Procedure for theReed-Solomon Codes, "NASA Technical Paper 1286, 1978 pp. 12-15. FIG. 3depicts prior-art circuitry implementing equation (4), comprising d-1registers 113 denoted D(0) through D(d-2); d-1 constant finite-fieldmultipliers 110 implementing multiplication by α^(j) for j from 0 tod-2; d-1 three-input multiplexers 111; and a (d-1)-input EXCLUSIVE-ORcircuit 112. All registers, multiplexers, multipliers and data paths aresymbol wide.

In the operation of FIG. 3, first the following process is repeated d-1times for j from 0 to d-2: present coefficient R_(j) and assert controlsignal LD₋₋ D(j) to store R_(j) in D(j). Then control signal EN isasserted and the following process is repeated d-1 times for i from 0 tod-2: syndrome S_(i) is produced on OUT and stored elsewhere and theoutputs of multipliers α^(j) 110 are stored in respective registers D(j)113 for j from 0 to d-2.

The circuit of FIG. 3 is undesirable because it requires an excessivenumber of registers and constant finite-field multipliers and a verylarge EXCLUSIVE-OR circuit. Thus it is clear that improved methods forcomputing frequency-domain syndromes are needed.

ITERATIVE ALGORITHM

Iterative algorithms for generating the error locator polynomial forReed-Solomon and related codes are known in the art; see Clark and Cain,Error Correction Coding for Digital Communications, 1981, pp. 204-208.Iterative algorithms which require no inversion are also known in theart; see Burton, "Inversionless Decoding of Binary BCH Codes," IEEETransactions on Information Theory, IT-17, 1971, pp. 464-466. FIG. 4shows the steps of a prior-art inversionless iterative algorithm. Instep 1, counters n, k and L, parameter d_(k) and polynomials σ.sup.(n)and σ.sup.(k) are initialized. In step 2, the nth discrepancy d_(n) iscalculated. If d_(n) is zero, control passes to step 6. Otherwise, step3 calculates the updated error locator polynomial σ.sup.(p). Then ifcounter L is greater than or equal to the difference n-k, control ispassed to step 5. Otherwise step 4 updates counters k and L, copiesd_(n) to d_(k) and copies σ.sup.(n) to σ.sup.(k). Step 4 copiesσ.sup.(p) to σ.sup.(n). Step 6 multiplies σ.sup.(k) by x and incrementscounter n. Then if counter n is less than 2·t, control is passed to step2. Otherwise, the iterative algorithm has been completed and σ.sup.(n)is the desired error locator polynomial. The prior-art iterativealgorithm of FIG. 4 is undesirable because it requires storage elementsfor three polynomials and repeated copying of polynomial coefficientsfrom one storage area to another.

FINITE-FIELD COMPUTATIONS

Hardware capable of performing the computations required for decodingReed-Solomon and related codes are known in the art; see Glover andDudley, Practical Error Correction Design for Engineers, 1988, page 353.FIG. 5 shows the major blocks of a prior-art decoding circuit comprisingsyndrome generator 180; syndrome buffer 181; work buffer 182; sequencer183; registers 195 A, B, C, D, E, F, G and H; read-only-memory tables184; EXCLUSIVE-OR circuit 185; zero-detection circuits 186 and 187;finite-field logarithm read-only-memories 188 and 189; NOR circuit 190;ones-complementing circuit 191; modulo-255 adder 192; finite-fieldantilogarithm table 193; and gating circuit 194. Unless otherwise noted,all paths are eight bits wide.

In operation of FIG. 5, syndrome generator 180 generatesfrequency-domain syndromes for all interleaved codewords simultaneouslyand stores them in syndrome buffer 181. Sequencer 183 controls theoperation of the decoder, using work buffer 182 to store intermediateresults produced using the other circuitry. Finite-field sums areproduced using EXCLUSIVE-OR circuit 185. Finite-field variable productsare produced using logarithm tables 188 and 189, adder 192,antilogarithm table 192, zero-detection circuits 186 and 187, NORcircuit 190 and gating circuit 194. Finite-field inversion is performedusing read-only memory tables 184.

The circuitry of FIG. 5 is undesirable because it requires an excessiveamount of complex and relatively slow circuitry. Syndrome generator 180contains separate syndrome computation circuits for each interleavedcodeword. The finite-field computation circuit contains a large numberof registers. The read-only-memory circuits of 184, 188, 189 and 192 areboth complex and slow, limiting the maximum rate of operation. It isclear that less expensive, faster circuitry is needed.

CRC RESIDUE ADJUSTMENT

The ANSI/ISO standards for 90 mm and 130 mm optical disk media providefor a CRC code covering all interleaves of the user data and thevendor-unique/pointer information bytes. This distance-five,Reed-Solomon code has information symbols comprising the EXCLUSIVE-ORsum of bytes across interleaves. The CRC code generator polynomial GC(x)is of degree four: ##EQU5## where dc is the degree and c is the offsetof the CRC code generator polynomial. The time-domain CRC residuepolynomial RC(x) has coefficients RC_(j) defined by ##EQU6## whereCC'(x) is the received CRC codeword polynomial. The residue of this codemust be adjusted to remove the contribution of each identified error.After all errors have been identified, the adjusted CRC residue must bezero; if not, a miscorrection of an uncorrectable error by the errorcorrection code has been detected.

One method for adjusting the CRC residue is to re-encode the sectorafter the error detection, identification and correction process hasbeen completed and check that the re-encoded CRC redundancy symbolsmatch the corrected CRC redundancy symbols. This method is undesirablebecause it requires additional hardware to provide access to thecorrected data and additional time to perform the re-encoding process.

Another method for adjusting the CRC residue is to compute CRC syndromesSC_(c+i) from CRC residue coefficients RC_(j) according to: ##EQU7## andthen adjust the CRC syndromes according to: ##EQU8## where N is thetotal number of errors in symbols covered by the CRC code, E_(j) are theerror values and L_(j) are the locations of the errors relative to theCRC code. This method is undesirable because it requires additional timeto compute the CRC syndromes and to perform the adjustment. It is clearthat faster and less expensive methods for adjusting the CRC residue areneeded.

SUMMARY OF THE INVENTION

Apparatus and methods are disclosed for providing an improved system foridentifying the location and value of errors introduced in binary dataencoded using Reed-Solomon and related codes and to detectmiscorrections of such codes with an auxiliary code. The inventionemploys an architecture based on a microcode engine that is specializedfor error identification and that supports interleaved codewords. Thisarchitecture can be efficiently fabricated as an integrated circuit, yetis capable of identifying multiple introduced errors "on the fly" i.e.with performance sufficient to not significantly slow the process ofreading from data storage or transmission subsystems such as, but notlimited to, optical disks. In the preferred embodiment, a new two-stepmethod of error syndrome computation is employed to reduce circuit costand complexity. An improved iterative algorithm is provided whichreduces circuit cost and complexity and decreases the time required togenerate the error locator polynomial. Cyclic redundancy check (CRC)information is adjusted as introduced errors are identified during theChien search, thus reducing the time required to protect against ECCmiscorrection. Externally-specified error thresholds allow detection ofexcessive numbers of errors.

In accordance with the foregoing, an object of the present invention is,in the typical case, to identify a plurality of errors introduced withina particular sector during the time period in which the next adjacentsector is being read or received from the storage or transmissionmedium. In the atypical case where the time required to identify thenumber of introduced errors exceeds the time required to read the nextadjacent sector, or where the number of introduced errors exceeds eitheran externally specified threshold or the correction power of thespecific Reed-Solomon code used, the present invention detects thiscase, signals an external microcontroller and signals the ENDEC sectionof the CL-SM330 to cease reading the medium.

Another object of the present invention is to reduce the implementationcost and complexity of error identification circuitry by performingerror syndrome computation in two steps, where each step processes halfof the required bits through a finite-field computation circuit ofapproximately half the size required by the prior-art one-step method.

Another object of the present invention is to provide an enhancement ofthe prior-art iterative algorithm to allow computing the coefficients ofthe error locator polynomial in a manner that is quicker and requiresless circuitry than prior-art implementations by using two polynomialsand by interchanging the values of two pointers to two tables containingthe coefficients of these polynomials and interchanging their associatedparameters.

Another object of the present invention is to reduce the time requiredby the error identification computation by performing, during the Chiensearch for introduced errors, the required adjustment of the CRCinformation whenever an error is identified. Data paths and computationcircuits are provided specifically to support this objective.

Another object is to provide an architecture particularly suitable forerror identification computations which includes both a specializeddata-path design and a set of specialized microengine instructions andwhich is suitable for implementation in an integrated circuit.

Another object is to provide elements of the set of microengineinstructions which efficiently control the execution of finite-fieldvariable multiply-and-sum operations.

Another object of the present invention is to accept time-domain errorsyndromes so as to support a high performance, cost-efficientimplementation for Reed-Solomon codes that allows the same LFSR to beused for both encoding and decoding of Reed-Solomon codewords.

Another object is to support the ANSI/ISO standard formats for both512-byte and 1024-byte sector sizes and both 90 mm and 130 mmoptical-disk medium sizes.

Another object is to allow the code symbols of the informationpolynomial to be interleaved, as is known in the art, among a pluralityof codeword polynomials, each containing its own independent redundancypolynomial while using the same error identification circuitry for eachinterleave.

Another object is to allow the EXCLUSIVE-OR sum across interleaves ofthe code symbols of the information polynomial to form the informationsymbols of a codeword of an overlay CRC code.

Another object is to adjust this CRC information as errors are detectedduring the Chien search, thus reducing the time required to protectagainst ECC miscorrrection.

Another object is to detect when the number of errors identified withina sector exceeds externally specified thresholds.

These and other objects of the invention will become apparent from thedetailed disclosures following herein.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates the ANSI standard layout of a sector containing 512user data bytes on 90 mm Continuous Composite Servo (CCS) optical-diskmedia.

FIG. 2 illustrates the ANSI standard layout of the data area within asector containing 512 user data bytes on 90 mm CCS optical-disk media.

FIG. 3 is a logic diagram of a prior-art syndrome computation circuitthat outputs one syndrome per clock cycle.

FIG. 4 is a flow chart of a prior-art iterative algorithm for computingthe coefficients of the error locator polynomial.

FIG. 5 is a block diagram of a prior-art circuit for performingfinite-field computations.

FIG. 6 is a block diagram of an optical-disk data-storage systemcontaining the present invention.

FIG. 7 is a block diagram of the CL-SM330 portion of the optical-diskdata-storage system.

FIG. 8 is a block diagram of the CL-SM331 portion of the optical-diskdata-storage system.

FIG. 9 is a logic diagram of a new two-step syndrome computationcircuit.

FIG. 10 is a logic diagram of a two-step syndrome computation circuitequivalent to that of FIG. 9 except for the constant finite-fieldmultipliers implemented.

FIG. 11 is a logic diagram of circuit which can be shared for two-stepsyndrome computation and for finding the roots of the error locatorpolynomial.

FIG. 12 is a logic diagram of another circuit which can be shared fortwo-step syndrome computation and for finding the roots of the errorlocator polynomial.

FIG. 13 is a flow chart of a new iterative algorithm for computing thecoefficients of the error locator polynomial.

FIG. 14 is a high-level block diagram of the CL-SM330's ECC/CRC blockcontaining the error identification circuit of the present invention andshowing its interfaces with the other blocks of the CL-SM330.

FIG. 15 is a register address and bit assignment map of the interfacebetween the error identifier circuit and the external microcontroller.

FIG, 16 is block diagram of the error identification circuit of thepresent invention showing its major functional blocks.

FIG. 17 is a block diagram of the Address Pointer Circuit (APC) block ofthe present invention.

FIG. 18 is a block diagram of the CRC Residue Adjuster (CRA) block ofthe present invention.

FIG. 19 is a block diagram of the Error Vector Control (EVC) block ofthe present invention.

FIG. 20 is a block diagram of the Frequency Domain Circuit (FDC) blockof the present invention.

FIG. 21 is a block diagram of the Finite Field Processor (FFP) block ofthe present invention.

FIG. 22 is a logic diagram of the finite-field Variable Multiply-and-Sum(VMS) circuit of the present invention.

FIG. 23 is a block diagram of the Instruction Processing Circuit (IPC)block of the present invention.

FIG. 24 is a block diagram of the Interleave & Sector Counters (ISC)block the present invention.

FIG. 25 is a flow chart of the overall read sector operation.

FIG. 26 is a flow chart of the identify errors operation.

FIG. 27 is a flow chart of the initialize RAM and CRA operation.

FIG. 28 is a flow chart of the compute frequency-domain syndromesoperation.

FIG. 29 is a flow chart of the compute error locator polynomialcoefficients operation.

FIG. 30 is a flow chart of the find errors and adjust CRC residueoperation.

DESCRIPTION OF THE PREFERRED EMBODIMENT SYSTEM DESCRIPTION

FIG. 6 is a block diagram of an optical disk system for data storagethat embodies the present invention within the CL-SM330 integratedcircuit. The CL-SM330 and CL-SM331 are a set of two high-integration,integrated circuits for optical disk controllers for embedded controllerapplications. They fully support the ANSI/ISO industry standard opticaldisk formats using the CCS (Continuous Composite Servo) standard forboth 90 mm (3.5") and 130 mm (5.25") optical disk drives. Therewritable, partial ROM and WORM (Write Once Read Many) standards aresupported. The high integration and optimized pin-out of theCL-SM330/331 make them suitable for embedded controller applications,particularly for 90 mm drives where only limited board space isavailable. The CL-SM330 Optical Disk ENDEC/ECC implements theencoder/decoder/formatter and the error detection, identification andcorrection logic required by the CCS standard. The CL-SM331 SCSI OpticalDisk Controller implements a Small Computer System Interface (SCSI),Buffer Manager and Sector formatter. The CL-SM330 and CL-SM331, alongwith buffer memory, a data separator and a local microcontroller withsystem Read-Only-Memory and Random-Access-Memory, complete ahigh-performance, low-cost optical disk controller subsystem.

A local microcontroller provides both the CL-SM330 and the CL-SM331 withinitial operating parameters, such as disk sector format, type and sizeof buffer memory and SCSI host controller. During data transferoperations, the CL-SM330/331 require only minimal intervention from thelocal microcontroller. Features such as auto-incrementing ID registersand fully-automated error correction (in typical cases) minimize themicrocontroller's real-time interaction with disk activity.

FIG. 7 is a block diagram of the CL-SM330 integrated circuit showing itsinterfaces to the CL-SM331, the microcontroller, and the optical drive,as well as its ENDEC and ECC/CRC circuits. The present invention is partof the ECC/CRC block shown. The microcontroller-to-CL-SM330communication path is a multiplexed address and data path similar tothat provided by Intel 80188 and Motorola 68HC11 classes ofmicrocontrollers. A configuration pin is available to allow selection ofthe microcontroller-bus control-signal method of either class. Virtuallyall controller functions are programmable by the microcontroller viaread/write registers. This provides substantial firmware control overdrive operation to allow for various retry methods and other uniquerequirements. The CL-SM330 has centralized status registers withinterrupt capability. These features allow firmware designersflexibility in writing polled loops or interrupt handlers to providereal-time process control critical in embedded controller driveapplications.

The data interface between the CL-SM330 and CL-SM331 is a serial NRZinterface. NRZ data is transmitted between the two devices with theRead-Reference Clock (RRCLK). Disk interface control signals, such as"Sector Mark Found" "ID Found" etc., are used for synchronization of thedata transfer between the CL-SM330 and CL-SM331. A dedicated serialError Vector Interface transfers error correction vectors with theSystem Clock (SYSCLK) to the CL-SM331 for actual correction of erroneousbytes in the buffer. To protect against errors in the informationtransmission between the two devices, eight-bit checksums cover allinformation transferred over the NRZ Interface and the Error VectorInterface. An Interrupt line allows optional connection of the CL-SM331and CL-SM330 interrupt mechanisms, resulting in a single interrupt lineto be handled by the local microcontroller.

The CL-SM330 supports standard 512-user-data-byte sectors with five ECCinterleaves or 1024-user-data-byte sectors with ten ECC interleaves.Correction of erroneous data in the buffer is performed by theCL-SM330/331 controller independent of the microcontroller. All butworst-case errors are corrected "on-the-fly", without loss of diskrevolutions. "On-the-fly" operation is achieved by identifying theintroduced errors using the present invention and generating errorcorrection vectors for each sector while the next adjacent sector isbeing read by the controller. Error correction vectors are transmittedto the CL-SM331 through the dedicated serial Error Vector Interface. Anindependent Corrector Clock input (CORRCLK) is provided for the ECC/CRCblock to allow optimum error identifier performance, independent of theSystem Clock frequency. Overlay CRC verification is performed inhardware during the error identification process, resulting in very lowmiscorrection probability without significant performance penalty.

The CL-SM330 ENDEC section includes the RLL (2,7) encoder/decoder andcircuitry for the generation and detection of the special marks requiredby the optical disk format. Full ANSI/ISO format support provides forprogrammable Sector Mark, ID Field, Data Sync Mark and Resync Markthresholds, as well as automatic hardware PLL synchronization andre-synchronization capability, compensation for Sector Mark asymmetry,Flag generation and written Flag detection. Output signals are providedto indicate the position of the Pre-Formatted data area, the TrackOffset Flag area and the Automatic Laser Power Control area.

The data connection from the CL-SM330 to the optical drive is a serialRLL (2,7) encoded interface. Output signals are also provided for datasynchronizer (PLL) control; during either normal phase lock or, if phaselock is lost while reading, these signals can be used to control thesynchronization or resynchronization of the phase-locked loop to theincoming data stream. A general-purpose eight-bit output port and ageneral-purpose eight-bit input port, as well as two general purposeinterrupt inputs, are available on the CL-SM330 to allow customizationof the drive interface and minimize external component requirements.

FIG. 8 is a block diagram of the CL-SM331 integrated circuit includingits interfaces with the SCSI bus and the microcontroller, Buffer Managerand Differential Control circuits, as well as its Format Sequencer andassociated Writable Control Store (WCS) and Sector Formatter Data Path.The CL-SM331 Microcontroller Interface is similar to that of theCL-SM330 Microcontroller Interface, with the addition of a Ready signalwhich enables the CL-SM331 to force wait states on the microcontrolleraddress/data bus.

The CL-SM331 SCSI is designed for compliance with the SCSI-IIspecification; see Small Computer Standard Interface-2 Draft ProposedAmerican National Standard, XT9.2/86-109 Rev. 10c, X3.131-199x, Mar. 9,1990. The SCSI logic includes integrated 48 mA drivers for thesingle-ended option as well as signals for control of the external logicnecessary to implement the differential transceiver option. Both theasynchronous and synchronous transfer protocols are supported in eitherInitiator or Target mode. Routine bus control operations such asarbitration, selection and reselection are automatically sequenced inhardware. This method of implementing the SCSI Interface makes the SCSIprotocol firmware extremely flexible and very efficient.

The CL-SM331 Buffer Manager controls the flow of data between the SCSIand disk interface. These interfaces store and retrieve data from thebuffer memory using interleaved access cycles. The actual buffer memorymay be implemented with static or dynamic RAM devices. The CL-SM331Buffer Manager is programmable to provide all of the necessary addressand control signals for RAM devices of varying access times. Up to 256KBytes of SRAM can be directly addressed by the CL-SM331. As much as 4MBytes of DRAM is directly supported by the CL-SM331 with specificcontrol for 64 Kbit, 256 Kbit, 1 Mbit and 4 Mbit devices. In DRAM mode,refresh cycles are generated automatically through a third channel tothe buffer memory in addition to the concurrent disk and SCSI accesses.The CL-SM331 Buffer Manager accepts error correction vectors from theCL-SM330 chip and automatically corrects errors in the buffer RAM withno interruption of the current data transfer.

The CL-SM331 Format Sequencer, WCS and Sector Formatter Data Path blocksprovide for interface between the CL-SM331 and CL-SM330, as describedabove. The Data Path logic performs the serial-to-parallel andparallel-to-serial conversion for NRZ data transfer between the bufferand the CL-SM330. The Format Sequencer controls the low-level sectorformat control, as defined by the pattern loaded in the WCS.

TWO-STEP SYNDROME COMPUTATION

Define x as the largest integer not greater than x and define t= (d-1)/2.

Equation (3) can be written as ##EQU9##

From equation (9) it is clear that the computation of frequency-domainsyndromes S_(m+i) can be performed in two steps wherein one stepproduces values A_(m+i), the other step produces values B_(m+i), andsyndromes S_(m+i) are formed as the EXCLUSIVE-OR sums of respectivevalues A_(m+i) and B_(m+i).

The circuitry of FIG. 9 implements equation (9) for codes with odd d; itcomprises t registers 127 denoted D(0) through D(t-1); t constantfinite-field multipliers 120 implementing multiplication by α^(j) for jfrom 0 to t-1; t three-input multiplexers 121; register 128 DM; aconstant finite-field multiplier 122 implementing multiplication byα^(m) ; a t-input EXCLUSIVE-OR circuit 123; register 129 DT; a constantfinite-field multiplier 126 implementing multiplication by α^(t) ; andtwo variable finite-field multipliers 124 and 125. Multipliers 124 and125 may be implemented as one multiplier with appropriate multiplexingof inputs and output, which is preferred due to the circuitry cost ofvariable multiplexers. All registers, multiplexers, multipliers and datapaths are symbol wide. Values A_(m+i) are produced on OUT1 and valuesB_(m+i) are produced on OUT2.

In the first step of operation of FIG. 9, DM is initialized to α⁰, thenthe following process is repeated t times for j from 0 to t-1: presentcoefficient R_(j) and assert control signal LD₋₋ D(j) to store in D(j)the product of R_(j) and the output of DM, and store the output ofmultiplier 122 in DM. Then control signal EN is asserted and thefollowing process is repeated d-1 times for i from 0 to d-2: saveelsewhere value A_(m+i) on OUT1 and store the outputs of multipliers *α^(j) 120 in respective registers D(j) for j from 0 to t-1.

In the second step of operation of FIG. 9, DM is initialized to α^(t)·mand the following process is repeated t times for j from 0 to t-1:present coefficient R_(j+t) and assert control signal LD₋₋ D(j) to storein D(j) the product of R_(j+t) and the output of DM, and store theoutput of multiplier 122 in DM. Then DT is initialized to α⁰, controlsignal EN is asserted and the following process is repeated d-1 timesfor i from 0 to d-2: save as S_(m+i) the EXCLUSIVE-OR sum of valueB_(m+i) on OUT2 and value A_(m+i) from the first step, store the outputsof multipliers * α^(j) 120 in respective registers D(j) for j from 0 tot-1, and store the output of multiplier * α^(t) 126 in DT.

Using the circuit of FIG. 9, it is possible to reverse the order of thetwo steps, first processing R_(t) through R_(d-2) and then processing R₀through R_(t-1). In the first step of operation, initialize DM toα^(t)·m load registers D(j) while presenting R_(t) through R_(d-2), theninitialize DT to α⁰ and save elsewhere values B_(m+i) from OUT2. In thesecond step of operation, initialize DM to α⁰, load registers D(j) whilepresenting R₀ through R_(t-1), then save as S_(m+i) the EXCLUSIVE-OR sumof values A_(m+i) from OUT1 and respective values B_(m+i) from the firststep.

With a slight modification to the circuit of FIG. 9, it is possible toreverse the order in which the remainder coefficients R_(j) areprocessed within each step, in one step processing R_(d-2) through R_(t)and in the other step processing R_(t-1) through R₀. Replace multiplier122 with a multiplier implementing multiplication by α^(-m). In thefirst step of operation, initialize DM to α.sup.(d-2)·m, load registersD(j) while presenting R_(d-2) through R_(t), then initialize DT to α⁰and save elsewhere values B_(m+i) from OUT2. Then in the second step ofoperation, initialize DM to α.sup.(t-1)·m, load registers D(j) whilepresenting R_(t-1) through R₀, then save as syndromes S_(m+i) theEXCLUSIVE-OR sums of values A_(m+i) from OUT1 and respective valuesB_(m+i) from the first step. Alternatively, in the first step ofoperation, initialize DM to α.sup.(t-1)·m and load registers D(j) whilepresenting R_(t-1) through R₀, then initialize DT to α⁰ and saveelsewhere values B_(m+i) from OUT2. Then in the second step ofoperation, initialize DM to α.sup.(d-2)·m, load registers D(j) whilepresenting R_(d-2) through R_(t), then save as syndromes S_(m+i) theEXCLUSIVE-OR sums of values A_(m+i) from OUT1 and respective valuesB_(m+i) from the first step.

When d is even, the equation for values B_(m+i) becomes ##EQU10## andthe circuit of FIG. 9 is modified to include a register D(t) and anotherconstant finite-field multiplier 120 implementing multiplication byα^(t) and another three-input multiplexer 121, all connected as forexisting registers D(j), multipliers 120 and multiplexers 121.EXCLUSIVE-OR circuit 123 becomes a (t+1)-input EXCLUSIVE-OR circuit.Operation is modified to load register D(t) with zero before producingvalues A_(m+i) and with R₂·t before producing values B_(m+i). Remaindercoefficients may be processed in reverse order by performing the samemodification described above.

When d is even, it is possible to compute the syndromes in two stepswherein one step processes remainder coefficients R_(j) for j from 0 tot and the other step processes coefficients R_(j) for j from t+1 to d-2.To do so requires only replacing multiplier 126 with a multiplierimplementing multiplication by α^(t+1). D(t) is loaded with R_(t) beforeproducing values A_(m+i) and with zero before producing values B_(m+i).

Equation (3) can also be written as ##EQU11##

From equation (10) it is clear that the computation of frequency-domainsyndromes S_(m+i) can be performed in two steps wherein one stepproduces values A_(m+i), the other step produces values B_(m+i), andsyndromes S_(m+i) are formed as the EXCLUSIVE-OR sums of respectivevalues A_(m+i) and B_(m+i).

The circuitry of FIG. 10 implements equation (10) for codes with odd d;it comprises t registers 137 denoted D(t) through D(2·t-1); t constantfinite-field multipliers 130 implementing multiplication by α^(j) for jfrom t to 2·t-1; t three-input multiplexers 131; register 138 denotedDM; a constant finite-field multiplier 132 implementing multiplicationby α^(m) ; a t-input EXCLUSIVE-OR circuit 133; register 139 denoted DT;a constant finite-field multiplier 136 implementing multiplication byα^(-t) ; and two variable finite-field multipliers 134 and 135.Multipliers 134 and 135 may best be implemented as one multiplier withappropriate multiplexing of inputs and output. Values A_(m+i) areproduced on OUT2 and values B_(m+i) are produced on OUT1.

In the first step of the operation of FIG. 10, DM is initialized to α⁰and the following process is repeated t times for j from t to 2·t-1:present coefficient R_(j-t) and assert control signal LD₋₋ D(j) to storethe product of R_(j-t) and the output of DM in D(j), and store theoutput of multiplier * α^(m) 132 in DM. Then DT is initialized to α⁰control signal EN is asserted and the following process is repeated d-1times for i from 0 to d-2: save elsewhere value A_(m+i) from OUT2, storethe outputs of multipliers * α^(j) 130 in respective registers D(j) forj from t to d-2, and store the output of multiplier * α^(-t) 136 in DT.

In the second step of operation of FIG. 10, DM is initialized to α^(t)·mand the following process is repeated t times for j from t to 2·t-1:present coefficient R_(j) and assert control signal LD₋₋ D(j) to storethe product of R_(j) and the output of DM in D(j), and store the outputof multiplier 132 α^(m) in DM. Then control signal EN is asserted andthe following process is repeated d-1 times for i from 0 to d-2: save asS_(m+1) the EXCLUSIVE-OR sum of value B_(m+i) from OUT2 and valueA_(m+i) from the first step and store the outputs of multipliers α^(j)130 in respective registers D(j) for j from t to d-2.

Using the circuit of FIG. 10, it is possible to reverse the order of thetwo steps, first processing R_(t) through R_(d-2) and then processing R₀through R_(t-1). In the first step of operation, initialize DM toα^(t)·m, load registers D(j) while presenting R_(t) through R_(d-2),then save elsewhere values B_(m+i) from OUT1. In the second step ofoperation, initialize DM to α⁰ load registers D(j) while presenting R₀through R_(t-1), then initialize DT to α⁰ and save as S_(m+i) theEXCLUSIVE-OR sum of values A_(m+i) from OUT2 and respective valuesB_(m+i) from the first step.

With a slight modification to the circuit of FIG. 10, it is possible toreverse the order in which the remainder coefficients R_(j) areprocessed within each step, in one step processing R_(d-2) through R_(t)and in the other step processing R_(t-1) through R₀. Replace multiplier132 with a multiplier implementing multiplication by α^(-m). In thefirst step of operation, initialize DM to α.sup.(d-2)·m, load registersD(j) while presenting R_(d-2) through R_(t), then save elsewhere valuesB_(m+i) from OUT1. In the second step of operation, initialize DM toα.sup.(t-1)·m load registers D(j) while presenting R_(t-1) through R₀,then initialize DT to α⁰ and save as syndromes S_(m+i) the EXCLUSIVE-ORsums values A_(m+i) from OUT2 and respective values B_(m+i) from thefirst step. Alternatively, in the first step of operation, initialize DMto α^(t)·m, load registers D(j) while presenting R_(t-1) through R.sub.0, then initialize DT to α⁰ and save elsewhere values A_(m+i) from OUT2.In the second step of operation, initialize DM to α.sup.(d-2)·m loadregisters D(j) while presenting R_(d-2) through R_(t), then save assyndromes S_(m+i) the EXCLUSIVE-OR sums of values B_(m+i) from OUT1 andrespective values A_(m+i) from the first step.

When d is even, the equation for values B_(m+i) becomes ##EQU12## andthe circuit of FIG. 12 is used. Operation is similar to that for FIG. 10except that register D(2·t) is loaded with zero before producing valuesA_(m+i) and with R₂·t before producing values B_(m+i). Remaindercoefficients may be processed in reverse order by modifying FIG. 12 in afashion similar to that described for FIG. 10.

When d is even, it is possible to modify the circuit of FIG. 12 tocompute the syndromes in two steps wherein one step processes remaindercoefficients R_(j) for j from 0 to t and the other step processescoefficients R_(j) for j from t+1 to d-2. To do so requires onlyreplacing multiplier 156 with a multiplier implementing multiplicationby α^(t+1). D(2·t) is loaded with R_(t) before producing values A_(m+i)and with zero before producing values B_(m+i).

In the preferred embodiment of the invention, the CL-SM330'sEncode/Decode LFSR block presents interleaved remainder coefficientsR_(j) sequentially from R_(d-2) of the first interleaved codeword to R₀of the last interleaved codeword, and these coefficients are stored inthe error identifier RAM in that order beginning at a fixed address.Further, the number of interleaved codewords can be either five or ten,so the address in the identifier RAM of coefficient R₀ of a codeword isnot fixed. Therefore it is desirable to use a syndrome computation whichaccepts the remainder coefficients in order from R_(d-2) to R₀ ; wherethe order of the two steps of syndrome computation is reversed and theorder in which the coefficients R_(j) are processed within each steps isreversed, i.e. in the first step, R_(d-2) through R_(t) are processed toproduce values B_(m+i) and in the second step, R_(t-1) through R₀ areprocessed to produce syndromes S_(m+i) as the EXCLUSIVE-OR sums ofrespective values A_(m+i) and B.sub. m+i.

SHARING ERROR LOCATION CIRCUITRY

Errors can be located by finding the inverse roots of the error locatorpolynomial ##EQU13## where e is the number of errors, 1≦e≦t. Observethat at a root α^(i) of σ(x), ##EQU14##

The roots of σ(x) can be found by successively evaluating σ(x) at allx=α^(i) for i from 0 to n-1, where n<2^(b) is the codeword length. Avalue of α^(i) for which σ(α^(i)) evaluates to zero is a root of σ(x),and (-i) is the corresponding error location. This method is known as aChien search.

The circuit of FIG. 11 can be shared for computing frequency-domainsyndromes according to equation (9) and for finding the roots of theerror locator polynomial σ(x) according to equation (12) for codes withodd d. FIG. 11 comprises t+1 registers denoted D(0) through D(t); t+1constant finite-field multipliers 140 implementing multiplication byα^(j) for j from 0 to t, t+1 three-input multiplexers 141; a symbol-widegating circuit 146; register DM; a constant finite-field multiplier 142implementing multiplication by α^(m) ; a (t+1)-input EXCLUSIVE-ORcircuit 143; and two variable finite-field multipliers 144 and 145.Multipliers 144 and 145 may best be implemented as one multiplier withappropriate multiplexing of inputs and output. All registers,multipliers, multiplexers and data paths are symbol wide. FIG. 11implements a reduction in circuitry which is possible when d is odd;when d is even the circuit of FIG. 9, modified for even d as describedabove, is used.

The computation of frequency-domain syndromes with the circuit of FIG.11 is performed in a fashion similar to that used for the circuit ofFIG. 9. Control signal GT is deasserted so that the output of gatingcircuit 146 is zero.

The search for the roots of σ(x) using the circuit of FIG. 11 isaccomplished by first loading coefficients σ_(j) into the e+1 registersD(e-j) for j from 0 to e and loading zero into registers the t-eregisters D(j) for j from e+1 to t. Control signal GT is asserted sothat the input of gating circuit 146 is passed to its output. Thefollowing process is repeated n times for i from 0 to n-1: if OUT1 iszero, a root has been found and the error location is i; to search foranother root, store the outputs of multipliers * α^(j) 140 in respectiveregisters D(j) for j from 0 to t.

Multiplying equation (12) by α^(i)·t and transforming j, we obtain##EQU15##

The circuit of FIG. 12 can be shared for computing syndromes accordingto equation (10) and for finding the roots of the error locatorpolynomial σ(x) according to equation (13). FIG. 12 comprises t+1registers 157 denoted D (t) through D(2·t); t+1 constant finite-fieldmultipliers 150 implementing multiplication by α^(j) for j from t to2·t; register 158 denoted DT; a constant finite-field multiplier 156implementing multiplication by α^(-t) ; t+1 three-input multiplexers151; register 159 denoted DM; a constant finite-field multiplier 152implementing multiplication by α^(m), a (t+1)-input EXCLUSIVE-0R circuit153; and two variable finite-field multipliers 154 and 155. Multipliers154 and 155 may best be implemented as one multiplier with appropriatemultiplexing of inputs and output. All registers, multipliers,multiplexers and data paths are symbol wide.

The computation of frequency-domain syndromes with the circuit of FIG.12 is performed in a fashion similar to that used for the circuit ofFIG. 10.

The search for the roots of σ(x) using the circuit of FIG. 12 isaccomplished by first loading the coefficients σ_(j-t) into the e+1registers D(e-(j-t)) for j from t to t+e and loading zero into the t-eregisters D(j) for j from t+e+1 to 2·t. The following process isrepeated n times for i from 0 to n-1: if OUT1 is zero, a root has beenfound and the error location is i; to search for another root, store theoutputs of multipliers * α^(j) 150 in respective registers D(j) for jfrom t to 2·t.

Circuitry for computing syndromes in two steps and performing the Chiensearch is implemented in the preferred embodiment as shown in FIG. 16,FIG. 20, and FIG. 21. The IDC block fetches instructions from the ROMand decodes them to generate control signals for the RAM and the otherblocks. Remainder coefficients R_(j) ; values B_(m+i) and syndromesS_(m+i) ; and error locator polynomial coefficients o_(j) are stored inthe RAM, with values B_(m+i) and syndromes S_(m+i) sharing the samestorage elements. Registers 192 denoted D(0) through D(8); multiplexers191 denoted M(0) through M(8); multipliers 193 denoted A(8) throughA(16); and EXCLUSIVE-OR circuit 194 denoted FX of FIG. 20 correspond toregisters D(t) through D(2·t); multiplexers 151; multipliers * α^(j) 150for j from t to 2·t; and EXCLUSIVE-OR circuit 153 of FIG. 12. Registers202 denoted A135L, multiplier 201 denoted A135, register 206 denoted D0,and multiplier 204 denoted A247 of FIG. 21 correspond to register DM,multiplier * α^(m) 152; register DT, and multiplier * α^(-t) 156 of FIG.12. Finite-field variable multiply-and-sum circuit 208 denoted VMS ofFIG. 21 corresponds to finite-field variable multipliers 154 and 155 ofFIG. 12 implemented as a single multiplier with multiplexed inputs andoutputs and the circuit which produces the syndromes S_(m+i) as theEXCLUSIVE-OR sums of corresponding values A_(m+i) and B_(m+i).

IMPROVED ITERATIVE ALGORITHM

FIG. 13 is a flow chart of the improved iterative algorithm of thepresent invention. In FIG. 13, the "++" operator exchanges the values oftwo variables and v_(d), v_(n) and v_(k) are arbitrary non-zeroconstants. In step 11, counters n, l_(k) and l_(n) ; parameter d_(k) ;and polynomials σ.sup.(k) and σ.sup.(n) are initialized. In step 12,σ.sup.(k) is multiplied by x and the nth discrepancy d_(n) iscalculated. If d_(n) is zero, control passes to step 15. Otherwise, ifcounter l_(k) is less than or equal to the counter l_(n), control ispassed to step 14. Otherwise step 13 exchanges the values of countersl_(k) and l_(n) ; exchanges the values of parameters d_(k) and d_(n) ;and exchanges the values of σ.sup.(k) and σ.sup.(n) by exchanging theaddresses of σ.sup.(k) and σ.sup.(n). Step 14 updates error locatorpolynomial σ.sup.(n). Step 15 increments counter n. Then if counter n isless than t+l_(n), control is passed to step 12. Otherwise, theiterative algorithm has been completed and σ.sup.(n) is the desirederror locator polynomial.

The improved iterative algorithm reduces implementation complexity andcost by requiring only two polynomial coefficient storage areas, insteadof three, and decreases the time needed to compute the error locatorpolynomial by eliminating the need to copy polynomial coefficients fromone storage element to another. The improved iterative algorithm isparticularly suited for implementation in hardware, where exchanging thevalues of two variables is simply accomplished by cross-connecting theoutputs and inputs of two registers which contain the values, or, as inthe case of variables stored in a random-access memory, of two registerswhich contain the addresses of the memory elements which contain thevalues.

In the preferred embodiment of the invention, implementation complexityis reduced and speed of operation is increased by storing thecoefficients of each polynomial σ.sup.(n) and σ.sup.(k) in a number ofmemory elements equal to 2·t+1 wherein the first t and last t elementsare initially cleared to zero and the middle element is initialized toan arbitrary non-zero constant. The coefficients of polynomialsσ.sup.(n) and σ.sup.(k) are stored in order of increasing degree of x.The operation of multiplying σ.sup.(k) by x is implemented bydecrementing a register containing the address of the low-ordercoefficient of σ.sup.(k). The operation of exchanging the coefficientsof σ.sup.(n) and σ.sup.(k) is implemented by exchanging the contents oftwo registers containing the addresses of the low-order coefficients ofσ.sup.(n) and σ.sup.(k). The operation of computing σ.sup.(n) = d_(k)*σ.sup.(n) ⊕d_(n) *σ.sup.(k) where l_(k) <l_(n) is performed in a looprepeated l_(n) times for i from 0 to l_(n) -1. This operation does notrequire any special treatment for those coefficients of σ.sup.(k) wherei>l_(k).

Circuitry for performing the new iterative algorithm of the presentinvention as implemented in the preferred embodiment is shown in FIG.16, FIG. 17, FIG. 21 and FIG. 23. Referring to FIG. 16, the IPC(Instruction Processing Circuit) block FIG. 23 fetches instructions fromthe ROM and controls the circuitry of the RAM, the APC (Address PointerCircuit) block FIG. 17 and the FFP (Finite Field Processor) block FIG.21. The RAM holds the value of counter n at location N; the syndromes,beginning at location S; and the coefficients of polynomials σ.sup.(k)and σ.sup.(n), low-order first beginning at the locations contained inregisters 175 denoted SK and 171 denoted SN of FIG. 17, respectively.Registers 277 denoted LK and 278 denoted LN of FIG. 23 contain thevalues of counters l_(k) and l_(n), respectively. Registers 203 denotedDK and 206 denoted D0 of FIG. 21 hold the values of parameters d_(k) andd_(n), respectively.

For step 1, LK and LN are cleared to zero, SK and SN are initialized,the locations in the RAM used for the coefficients of polynomialsσ.sup.(k) and σ.sup.(n) are initialized, DK is initialized to a non-zerovalue, and D1 is initialized to -(t-2). For step 2, location N in theRAM is written from D1, LK is incremented, σ.sup.(k) is multiplied by xby decrementing SK, D0 is cleared, and the nth discrepancy d_(n) iscalculated by using the VMS Variable Multiply-and-Sum block of FIG. 21to sum into DO the products of the contents of the RAM elements pointedto by SN and the syndromes in the area in the RAM beginning at locationS. The block 274 denoted M40 of FIG. 23 is used to determine ifparameter d_(n) is zero; if so, control passes to step 5. Otherwise,block 212 denoted ADD (Integer Addition Circuit) (FIG. 21) and block 270denoted AGZ (Greater-than-Zero) Detection Circuit) (FIG. 23) are used todetermine if the contents of LK are less than or equal to the contentsof LN; if so, control is passed to step 14. Otherwise for step 13, thecontents of LK and LN are exchanged; the contents of DK and D0 areexchanged; and the contents of SK and SN exchanged. For step 14, thecoefficients of polynomial σ.sup.(n) are updated by using the VMS blockof FIG. 21 to sum the products of the contents of DK and the contents ofthe RAM elements pointed to by SK with the products of the contents ofD0 and the contents of the RAM elements pointed to by SK using the VMSblock of FIG. 21 and then storing the results into the RAM elementspointed to by SN. For step 15, the ADD block of FIG. 21 and the AGZblock of FIG. 23 are used to determine if the sum of the contents of D1and the contents of LN is less than or equal to zero; if so, the ADDblock of FIG. 21 is used to form in D1 the sum of one and the contentsof the RAM at location N, and control is passed to step 2. Otherwise,the iterative algorithm has been completed; LN holds the degree and SNholds the address in the RAM of the coefficients of the error locatorpolynomial σ.sup.(x).

CONCURRENT CRC RESIDUE ADJUSTMENT

In the preferred embodiment of the invention, the adjustment of the CRCinformation required whenever an error is identified is performed duringthe Chien search. Circuitry for performing the CRC residue adjustment asimplemented in the preferred embodiment is shown in FIG. 18, FIG. 21,and FIG. 23.

The CRC residue is adjusted in a dedicated CRC Residue Adjuster (CRA)comprising a Linear Feedback Shift Register (LFSR) implementing thereciprocal of the CRC code generator polynomial. The registers in theCRA are initially loaded with the CRC residue symbols. Referring to FIG.18, loading the CRA registers is performed by asserting control signalEN and deasserting control signals SH and FB while presenting the CRCresidue symbols on RAM₋₋ OUT, most-significant symbol first.

The search for roots α^(i) of the error locator polynomial is performedsequentially for all i from 0 to n. For each interleave in error, beforethe search for roots reaches i equal to d-1, zero is clocked into theCRA x times, where x is the non-inclusive number of CRC redundancysymbols between the last non-ECC-redundancy symbol of the interleave inerror and the first ECC redundancy symbol of the first interleave. Forexample, referring to FIG. 2, x is equal to 4, 3, 2, 1 and 0 for theinterleaved codewords containing the symbols labeled "VU4" "CRC1" "CRC2""CRC3" and "CRC4" respectively. Referring to FIG. 18, clocking a valueinto the CRA is performed by asserting control signals EN, SH and FB andpresenting the value on CRA₋₋ IN.

If a root is found for i equal to d-1, the error value is clocked intothe CRA; otherwise zero is clocked into the CRA. Then if the symbolcorresponding to i equal to d-1 is a CRC redundancy symbol, zero isclocked into the CRA y times where y is the non-inclusive number of CRCredundancy symbols between the symbol corresponding to i equal to d-1and the last non-CRC-redundancy symbol of the sector. For example,referring to FIG. 2, y is equal to 0, 0, 1, 2 and 3 for the interleavedcodewords containing the symbols labeled "VU4" "CRC1" "CRC2" "CRC3" and"CRC4" respectively. For all i greater than d-1, either zero or thevalue of the error in the symbol corresponding to i is clocked into theCRA.

After all n locations of an interleave in error have been processed, thecontents of the dc-1 CRA registers are shifted out of the CRA andEXCLUSIVE-OR-ed into dc-1 storage elements elsewhere, and the dc-1 CRAregisters are cleared to zero. Referring to FIG. 18, the contents of theCRA are shifted out and the CRA registers are cleared to zero byasserting control signals EN and SH and deasserting control signal FB.In the preferred embodiment, referring to FIG. 21, the contents of eachCRA register are presented in turn on CRA₋₋ OUT and, using the VMSblock, multiplied by AL₋₋ OUT and EXCLUSIVE-OR-ed with the contents ofthe corresponding RAM storage element presented on RAM₋₋ OUT, the resultbeing stored in D1 and then D1₋₋ OUT being back into the RAM storageelement. This procedure works because AL₋₋ OUT is always the same,α_(n-1), after each interleave has been processed, and the fact that theadjusted CRC residue bytes for each interleave have all been multipliedby a common non-zero factor is immaterial if the sum of all the adjustedCRC residue bytes is zero. Implementation complexity is reduced becauseno unique instruction or instruction exception condition need beimplemented.

After all interleaved codewords have been processed, the dc-1 storageelements are checked for zero. This is performed adding zero to eachaccumulated adjusted CRC residue byte using the ADD circuit of the FFPFIG. 21 and using the M40 OR circuit in the IPC FIG. 23 to detect anynon-zero value.

ERROR IDENTIFIER ARCHITECTURE

FIG. 14 shows the CL-SM330's ECC/CRC block, including the interfacesbetween the error identifier, the Encode/Decode LFSR block, and theother blocks of the CL-SM330. The CORRCLK (Correction Clock) signalclocks the synchronous logic of the error identifier. The fiveconfiguration signals SIZE, FORM, SUPP, DIAG and VU₋₋ PTR and the START,STOP, CONT and DISABLE signals are the outputs of registers in theCL-SM330's Microcontroller Interface block which are programmed by theexternal microcontroller. The BUSY, DONE, ECC₋₋ ERR, CRC₋₋ ERR, THR₋₋ERR and OVERRUN signals are applied to the CL-SM330's MicrocontrollerInterface block. MPU₋₋ BUS provides an address bus, a data bus, andread/write control signals for external microcontroller access to theerror identifier RAM and register AO. The RRCLK, CG₋₋ RG, RMNDR and T7signals are provided to the error identifier from the Encode/Decode LFSRblock. The VREADY signal is fed from the CL-SM331 Buffer Manager throughthe CL-SM330's SM331 Interface block to the error identifier. The SEND₋₋VEC signal and the FWD₋₋ OUT and D1₋₋ OUT buses are applied to theCL-SM330's SM331 Interface block.

SIZE and FORM determine the number of interleaves (hereafter abbreviatedas NUM₋₋ ILVS) and the total number of bytes in the sector (hereafterabbreviated as NUM₋₋ BYTS):

    ______________________________________                                        SIZE    FORM       NUM.sub.-- ILVS                                                                          NUM.sub.-- BYTS                                 ______________________________________                                        0       0          5          600                                             0       1          5          610                                             1       x          10         1200                                            ______________________________________                                    

SIZE, FORM, SUPP, DIAG and VU₋₋ PTR control assertion of SEND₋₋ VEC asdescribed below. Assertion of START forces the error identifier to beginidentifying errors using the current contents of RAM. If the erroridentifier is identifying errors, assertion of STOP forces the erroridentifier to cease identifying errors and to assert DONE. Assertion ofDISABLE prevents the error identifier from beginning to identify errorsat the trailing edge of CG₋₋ RG as described below.

FIG. 15 shows the register address and bit assignments for the signalsaccessible to the external microcontroller through the CL-SM330'sMicrocontroller Interface block. A number in hexadecimal notation isdenoted by appending h to it. Because the overall CL-SM330 busy statusis read from bit 6 at register 10h, BUSY is advantageously implementedto be read from bit 4 at address 10h. Because START is best implementedas an edge-triggered control signal and the "write" function of bit 4 ofregister 10h would otherwise be wasted, START is advantageouslyimplemented to be asserted by writing one to bit 4 at address 10h.Because the CL-SM330 is configured for Read Sector operations by writingbits 3-0 of register 10h, SUPP is advantageously implemented to besimultaneously (de)asserted by writing (zero)one to bit 3 at address10h. Placing the form factor, sector size and vendor-unique/pointercontrol signals in the same register allows all three to be controlledwith one microcontroller access; therefore VU₋₋ PTR is (de)asserted bywriting (zero)one to bit 5 at address 11h, FORM is (de) asserted bywriting (zero) one to bit 1 at address 11h, and SIZE is (de)asserted bywriting (zero)one to bit 0 at address 11h. Disabling the erroridentifier and enabling continuous sector read operation are seldom-usedfunctions, so it is preferred that they be placed in register 12h alongwith other relatively static CL-SM330 configuration signals; DISABLE is(de)asserted by writing (zero)one to bit 3 at address 12h and CONT is(de)asserted by writing (zero)one to bit 0 at address 12h. Because it isdesirable to control related functions by accessing a single address andother medium-related CL-SM330 microcontroller interrupts are enabled anddisabled through register 21h, it is implemented so that when one iswritten to bit 0 at address 21h, the CL-SM330's MicrocontrollerInterface block will assert an interrupt signal to the externalmicrocontroller when the error identifier asserts DONE. For ease ofmicrocontroller firmware implementation it is advantageous thatinterrupt status signals be read from the corresponding bits at anotheraddress, so DONE is read from bit 0 at address 23h. Placing the errorsignals for the error identifier in the same register with otherCL-SM330 error signals allows all to be read with one microcontrolleraccess; therefore ECC₋₋ ERR, CRC₋₋ ERR, THR₋₋ ERR and OVERRUN are readfrom bits 7, 6, 5 and 4, respectively, at address 30h. Grouping theerror identifier RAM address and data access address with the erroridentifier error access register yields a more logical organization ofthe CL-SM330 microcontroller address space, so A0 is written at address31h and the RAM element at the address in A0 is read or written byreading or writing address 32h. Because A0 is incremented each time themicrocontroller accesses the error identifier RAM, the microcontrollerfirmware is always certain of the value of A0, implementation cost isreduced by providing no path for the microcontroller to read thecontents of A0. There is normally no need to transfer error correctionvectors for errors in the ECC redundancy bytes, so DIAG isadvantageously implemented to be (de)asserted by writing (zero)one tobit 4 at address 3Fh, wherein other bits control other test modes of theCL-SM330.

FIG. 16 is a block diagram of the error identifier. The major blockscomprising the error identifier are the Address Pointer Circuit 165(APC), CRC Residue Adjuster 164 (CRA), Error Vector Control 166 (EVC),Frequency Domain Circuit 167 (FDC), Finite Field Processor 169, (FFP),Instruction Processing Circuit 162 (IPC), Interleave & Sector Counters163 (ISC), Random Access Memory 168 (RAM) and Read-Only Memory 161(ROM).

The output of a register or circuit is denoted by appending "₋₋ OUT" toits name. The input to a register or circuit is denoted by appending "₋₋IN" to its name. A number in hexadecimal notation is denoted byappending `h` to it. Where not otherwise indicated, control signalinputs to registers, multiplexers, etc. are driven from the appropriate"xxx₋₋ CTU" bus from the IPC block 162, FIG. 23.

In the preferred embodiment of the invention, each instruction isfetched from the ROM and stored in the seventeen-bit instructionregister (IR), then decoded from IR₋₋ OUT and executed during the nextclock cycle. By pipelining the instruction in this manner, it isimmediately available at the beginning of each cycle with no ROM-accessdelay. Also, the decoding of instruction bits required to select theproper address to be applied to the RAM address bus is performed usingROM₋₋ OUT rather than IR₋₋ OUT, and the selected address is stored inthe eight-bit RAM address register (RA) and applied during the nextcycle. By pipelining the RAM address in this manner, it is immediatelyavailable at the beginning of each cycle with no instruction-decodingdelay.

FIG. 17 is a block diagram of the Address Pointer Circuit (APC), whichcontrols the address and data input buses of the RAM and the loading ofFDC registers D(i). APC includes A0, A1, AM, D49, RA, RMX, SK and SN.

A0 is an eight-bit register 172 which can supply an address for indirectaccess to the RAM. A0 can be loaded from SN₋₋ OUT, from RAM₋₋ OUT, orfrom the external microcontroller data bus. Bits 7-5 of A0₋₋ IN areforced to zero when SN is the source. A0 can be incremented. NUM₋₋ ILVScan be added to A0.

A1 is a seven-bit register 176 which can supply an address for indirectaccess to the RAM or to the FDC registers D(i). A1 can be loaded fromSK₋₋ OUT or from ADD₋₋ OUT. Bits 7-5 of A1₋₋ IN are forced to zero whenSK₋₋ OUT is the source. A1 can be incremented or decremented.

AM is a three-input, eight-bit-wide multiplexer 173 which supplies inputto RA. Its inputs are A0₋₋ OUT, A1₋₋ OUT and bits 6-0 of ROM₋₋ OUT. Bit7 of AM₋₋ OUT is forced to zero when A1₋₋ OUT or ROM₋₋ OUT is theselected source.

D49 is a four-to-nine decoder 177 with enable. A1₋₋ OUT is applied toD49₋₋ IN. D49₋₋ OUT is applied to the LD₋₋ D(i) inputs of FDCmultiplexers M(i).

RA is an eight-bit register 174 which holds the address applied to theRAM address bus during the execution of an instruction. RA is loadedfrom AM₋₋ OUT.

RMX is a four-input, eight-bit wide multiplexer 178 which supplies inputto the RAM data bus. Its inputs are FDC₋₋ OUT, M3₋₋ OUT, CER₋₋ BUS andthe external microcontroller data bus.

SK is a five-bit register 175 which holds the address of the low-ordercoefficient of the σ.sup.(k) polynomial in the RAM. SK can be preset to0Eh or loaded from SN₋₋ OUT. SK can be decremented.

SN is a five-bit register 171 which holds the address of the low-ordercoefficient of the σ.sup.(n) polynomial in the RAM. SN can be preset to1Fh or loaded from SK₋₋ OUT.

FIG. 18 is a block diagram of the CRC Residue Adjuster (CRA), which is aLFSR implementing H(x), the reciprocal of the Reed-Solomon generatorpolynomial GC(x) for the ANSI/ISO standard CRC code. CRA comprises foureight-bit registers (185-188) denoted C0, C1, C2 and C3; the CMcomputation circuit 183, described below; a two input, eight-bit-widemultiplexer 184 deonted MX; a two input, eight-bit-wide EXCLUSIVE-ORcircuit 181 denoted EO; and an eight-bit gating circuit 182 denoted CG.The output of C3 is CRA₋₋ OUT. CRA₋₋ IN and CRA₋₋ OUT are applied to theinputs of EO. EO₋₋ OUT is applied to CG₋₋ IN. CG₋₋ OUT, C2₋₋ OUT, C1₋₋OUT and C0₋₋ OUT are applied to inputs A, B, C and D of CM,respectively. Outputs W, X and Y of CM are applied to C3₋₋ IN, C2₋₋ INand Cl₋₋ IN, respectively. Output Z of CM and RAM₋₋ OUT are applied tothe inputs of MX. MX₋₋ OUT is applied to CO₋₋ IN.

To "clock the CRA" means to perform the combination of actions specifiedby bits 4-1 of IR-OUT:

    ______________________________________                                        4321 ACTION                                                                   ______________________________________                                        xx0x Disable loading of C0, C1, C2 and C3; i.e. force                              control signal EN to zero.                                               xx10 If LOC.sub.-- GT16 is one, enable loading of C0, C1, C2 and                   C3; i.e. force control signal EN to one if and only if                        LOCGT.sub.-- 16 is one.                                                  xx11 Enable loading of C0, C1, C2 and C3; i.e. force                               control signal EN to one.                                                x0xx Force CG.sub.-- out to zero; i.e. force control signal FB to                  zero.                                                                    x1xx Pass CG.sub.-- IN to CG.sub.-- OUT; i.e. force control signal FB to           one.                                                                     0xxx If enabled as specified above, load C3, C2 and C1 from                        outputs W, X and Y of CM, respectively, and load C0                           from RAM.sub.-- OUT; i.e. force control signal SH to zero.               1xxx If enabled as specified above, load C3, C2, C1 and C0                         from outputs W, X, Y and Z of CM, respectively.; i.e.                         force control signal SH to one.                                          ______________________________________                                    

CM is a four-input, four-output, eight-bit-wide constant finite-fieldcomputation circuit with inputs A, B, C and D, and outputs W, X, Y andZ, which implements:

W=H₃ *A⊕B

X=H₂ *A⊕C

Y=H₁ *A⊕D

Z=H₀ *A

where H_(i) are the coefficients of H(x).

FIG. 19 shows Error Vector Control (EVC), which controls the assertionof SEND₋₋ VEC, the signal which initiates transfer of an errorcorrection vector to the CL-CSM331. Each time the error identifier haslocated and identified an introduced error, EVC examines theconfiguration signals and applies the selected condition to FWD₋₋ OUT.If FWD₋₋ OUT satisfies the condition, ECV asserts SEND₋₋ VEC, causingthe CL-SM331 Interface block to execute an error correction vectortransfer using the current values of FWD₋₋ OUT and D1₋₋ OUT.

    ______________________________________                                                                            FWD.sub.-- OUT                            SUPP  DIAG    VU.sub.-- PTR                                                                           SIZE  FORM  CONDITION                                 ______________________________________                                        1     x       x         x     x     NONE                                                                          ALLOWED                                   0     1       x         x     x     ALL                                                                           ALLOWED                                   0     0       0         0     x     <512                                      0     0       0         1     x     <1024                                     0     0       1         0     0     <520                                      0     0       1         0     1     <530                                      0     0       1         1     x     <1040                                     ______________________________________                                    

FIG. 20 is a block diagram of the Frequency Domain Circuit (FDC), whichis used to compute syndromes from the time-domain remainders and tosearch for the roots of the error locator polynomial. The FDC in thepreferred embodiment is a variation on the circuit shown in FIG. 12. TheFDC comprises nine eight-bit registers 192 denoted D(i) for i from 0 to8, each associated with a constant finite-field multiplier 193 denotedA(8+i) and a two-input, eight-bit-wide multiplexer 191 denoted M(i);plus a nine-input, eight-bit-wide EXCLUSIVE-OR circuit 194 denoted FX;and an eight-bit-input OR circuit FDO. The output of FX is FDC₋₋ OUT andis applied to FDO₋₋ IN. The output of each register D(i) is applied tothe input of A(8+i) and to one of the inputs of FX. The output of eachmultiplier A(8+i) is applied to one of the inputs of M(i). FDC₋₋ IN isapplied to the other input of each multiplexer M(i). The output of eachmultiplexer M(i) is applied to the input of respective register D(i).When FDC register D(i) is to be loaded from FDC₋₋ IN, signal LD₋₋ D(i)from D49₋₋ OUT is asserted. To "clock the FDC" means to record FDO₋₋ OUTin the FZD latch within the IAC; to load each register D(i) from theoutput of its associated finite-field multiplier A(i); to store ALPHA1₋₋OUT in the AL register within the FFP; to store A135₋₋ OUT in the A135Lregister within the FFP; and to load the FWD register within the ISCfrom SUB₋₋ OUT within the ISC.

FIG. 21 is a block diagram of the Finite-Field Processor (FFP), whichperforms integer addition and variable finite-field multiply-and-sumoperations. It includes A135, A135L, A247, ADD, AL, ALPHA1, D0, D1, DK,M1, M2, M3, M4, M5 and VMS. Except as noted, all data paths are 8-bitswide.

A135 is a constant finite-field multiplier 201 implementingmultiplication by α¹³⁵. A135L₋₋ OUT is applied to A135L.

A135L is an eight-bit multiplexed register 202 which holds X*α¹³⁵·L,where L is the number of times A135L has been clocked since it wasloaded with X from IR₋₋ OUT. The value loaded into A135L is multiplexedbetween A135₋₋ OUT and bits 7-0 of IR₋₋ OUT. A135L₋₋ OUT is applied toA135₋₋ IN and M1.

A247 is a constant finite-field multiplier 204 implementingmultiplication by α²⁴⁷. D0₋₋ OUT is applied to A247₋₋ IN. A247₋₋ OUT isapplied to M5.

ADD is a two-input, eight-bit-wide integer addition circuit 212 with aone-bit carry-in signal CI implementing S=A+B+CI. M1₋₋ OUT is applied toinput A. M2₋₋ OUT is applied to input B. Bit C of IR₋₋ OUT is applied toinput CI.

AL is an eight-bit register 210 which holds α^(L-1), where L is thenumber of times AL has been clocked since it was initialized to α⁻¹ byassertion of control input I. AL₋₋ OUT is applied to ALPHA1₋₋ IN and M2.AL can be initialized to α⁻¹ or loaded from ALPHA1₋₋ OUT.

ALPHA1 is a constant finite-field multiplier 209 implementingmultiplication by α¹. ALPHA1₋₋ OUT is applied to AL₋₋ IN.

D0 is an eight-bit register 206 which is used for many purposes. D0 canbe loaded from M5₋₋ OUT. D0₋₋ OUT is applied to M1, M2 and A247₋₋ IN.

D1 is an eight-bit register 214 which is used for many purposes. D1 canbe loaded from M4₋₋ OUT. D1₋₋ OUT is applied to M2, M3 and the SM331interface block.

DK is an eight-bit register 203 which is used to hold d _(k) and forother purposes. DK can be loaded from D0 ₋₋ OUT. DK ₋₋ OUT is applied toM1.

M1 is a six-input, eight-bit-wide invertible multiplexer 207 whichsupplies input to VMS and ADD. Its inputs are D0₋₋ OUT, DK₋₋ OUT, LN₋₋OUT, CRA₋₋ OUT, A135L₋₋ OUT and zero. Bits 7-4 of the LN₋₋ OUT input areforced to zero. If bits P and 7 of IR₋₋ OUT are set, each bit of M1₋₋OUT is inverted.

M2 is a seven-input, eight-bit-wide multiplexer 211 which supplies inputto VMS and ADD. Its inputs are D0₋₋ OUT, D1₋₋ OUT, LK₋₋ OUT, AL₋₋ OUT,RAM₋₋ OUT, FDC₋₋ OUT and bits 7-0 of IR₋₋ OUT. Bits 7-4 of the LK₋₋ OUTinput are forced to zero. Bit 7 of the IR₋₋ OUT input is replaced withbit 6 of IR₋₋ OUT.

M3 is a three-input, eight-bit-wide multiplexer 215 which supplies inputto VMS, CRA and RMX. Its inputs are D1₋₋ OUT, RAM₋₋ OUT and zero. M3₋₋OUT is CRA₋₋ IN.

M4 is a three-input, eight-bit-wide multiplexer 213 which supplies inputto M5, D1 and the nine FDC registers D(i). Its inputs are VMS₋₋ OUT,ADD₋₋ OUT and zero. M4₋₋ OUT is FDC₋₋ IN.

M5 is a two-input, eight-bit-wide multiplexer 205 which supplies inputto D0. Its inputs are M4₋₋ OUT and A247₋₋ OUT.

FIG. 22 is a block diagram of the finite-field Variable Multiply-and-Sumcircuit (VMS), which implements Z=(A*B)⊕C, which is computed accordingto: ##EQU16## VMS comprises a single-input, eight-output constantfinite-field multiplier circuit 221 denoted B07; eight eight-bit-widegating circuits 222 denoted VG(i); and a nine-input, eight-bit-wideEXCLUSIVE₋₋ OR circuit 223 denoted VX. B07 implements

    Z(i)=A*2.sup.i

for i from 0 to 7. Mi₋₋ OUT is applied to input A of VMS, which is inputA of B07. M2₋₋ OUT is applied to input B of VMS; each bit i of B isapplied to the control input G of respective gating circuit VG(i). Theeight outputs Z(i) of B07 are applied to the inputs of VG(i), whoseoutputs are applied to the first eight inputs of VX. M3₋₋ OUT is appliedto input C of VMS, which is the remaining input of VX.

Note that propagation delay from input B of VMS to VMS₋₋ OUT is lessthan that from input A of VMS to VMS₋₋ OUT. RAM access time can besignificantly longer than other circuit delays. In the preferredembodiment, the propagation delay from RAM₋₋ OUT to M2₋₋ OUT isminimized in preference to the propagation delays from the other inputsof M2 to M2₋₋ OUT, and M2₋₋ OUT is applied to input B of VMS rather thanto input A of VMS. This minimizes the total propagation delay when a RAMelement is applied to VMS and increases the maximum CORRCLK rate whichmay be applied to the error identifier.

FIG. 23 is a block diagram of the Instruction Processing Circuit (IPC),which controls the operation of other portions of the error identifier.IPC contains AGZ, FZD, GTZ, IA, ID, IM, IR, LA, LC, LK, LN, M40, NZR, XIand ZRO.

AGZ is an eight-bit greater-than-zero detection circuit block 270.Greater than zero means the most-significant bit is zero and at leastone other bit is non-zero. ADD₋₋ OUT is applied to AGZ₋₋ IN.

FDO is an eight-bit-input circuit (block 272). FDC₋₋ OUT is applied toFD0₋₋ IN.

FZD is a one-bit register (block 273) which records FDO₋₋ OUT wheneverthe FDC is clocked.

GTZ is a one-bit register (block 271) which records AGZ₋₋ OUT when eachinstruction is executed.

IA is an eight-bit register (block 203), which holds the address appliedto the ROM address bus. IA can be cleared to zero, incremented, andloaded from IM₋₋ OUT.

ID is the Instruction-bit Decoding network (block 291), which generatescontrol signals for the error identifier hardware, including but notlimited to multiplexer selection signals; register increment-enable,decrement-enable and write-enable signals; and RAM write-enable signals.ID decodes instruction bits from ROM₋₋ OUT and IR₋₋ OUT and controlsignals from the other blocks of IPC to produce control signals appliedto the other blocks of the error identifier on the buses labeled APC₋₋CTL, CRA₋₋ CTL, etc.

IM is a two-input, eight-bit-wide multiplexer (block 282) which suppliesinput to IA. Its inputs are LA₋₋ OUT and bits 7-0 of IR₋₋ OUT.

IR is a seventeen-bit register (block 280) which holds the instructionbeing executed. IR is loaded from ROM₋₋ OUT. Bits 16-13 of IR₋₋ IN canbe forced to zero to prevent execution of the next instruction bytransforming it into a NOP.

LA is an eight-bit register (block 281) which holds the address of thefirst instruction of a DO loop. LA can be loaded from bits 7-0 of IR₋₋OUT.

LC is a four-bit register (block 279) which holds the loop count duringexecution of a DO loop. It can be loaded from LN₋₋ OUT or from bits 12-9of IR₋₋ OUT.

LK is a four-bit register (block 277) which holds the degree of theσ.sup.(k) polynomial. LK can be incremented, cleared to zero, or loadedfrom LN₋₋ OUT.

LN is a four-bit register (block 288) which holds the degree of the σ(n)polynomial. LN can be cleared to zero or loaded from LK₋₋ OUT or frombits 3-0 of ADD₋₋ OUT.

M40 is an eight-bit-input OR circuit (block 274). M4₋₋ OUT is applied toM40₋₋ IN.

NZR is a one-bit latch (block 276) which is set if M40₋₋ OUT is one whena Load₋₋ FDC₋₋ Rem instruction is executed. NZR can be cleared.

XI is the external interface module (block 290). XI controls APC whenthe external microcontroller is accessing RAM and when CRC residue/ECCremainder bits are being stored in RAM. The XI block of the IPC managesthe interfaces to the external microcontroller and the rest of theCL-SM330.

The microcontroller can write register A0 and read or write RAM at theaddress contained in A0. Each time the microcontroller accesses RAM, XIincrements A0.

If at the leading edge of CG₋₋ RG, either CONT is asserted or BUSY isnot asserted, XI presets A0 to the value 3Eh and begins deserializingbits from RMNDR onto the eight-bit-wide CER₋₋ BUS. When T7 is assertedduring the last bit of each byte, XI stores the deserialized byte onCER₋₋ BUS into RAM at the address contained in A0 and then incrementsA0. In addition, if at the leading edge of CG₋₋ RG both CONT and BUSYare asserted, then XI asserts OVERRUN, stops and does not complete thecurrent error identification process.

If at the leading edge of CG₋₋ RG, CONT is not asserted and BUSY isasserted, then XI asserts OVERRUN, does not store the deserialized CRCresidue or ECC remainder bits in RAM, and does not stop the currenterror identification process.

If at the trailing edge of CG₋₋ RG, no non-zero bit was detected onRMNDR while CG₋₋ RG was asserted and either CONT is asserted or OVERRUNis not asserted, then XI asserts DONE.

If at the trailing edge of CG₋₋ RG, any non-zero bit was detected onRMNDR while CG₋₋ RG was asserted and DISABLE is not asserted and eitherCONT is asserted or OVERRUN is not asserted, then XI asserts BUSY andthe error identifier begins identifying introduced errors.

When a Stop instruction is executed, XI asserts DONE and stops the erroridentifier by deasserting BUSY, which forces IA to zero. If anuncorrectable ECC error, uncorrectable CRC error, or error exceedingthreshold has been detected, a Stop instruction will be executed whichcauses XI to assert ECC₋₋ ERR, CRC₋₋ ERR, or THR₋₋ ERR, respectively.

ZRO is a one-bit register (block 275) which records NOT(M40₋₋ OUT) wheneach instruction is executed.

FIG. 24 is a block diagram of the Interleave and Sector Counters (ISC)block, which maintains forward displacement and ECC error locationcounters for the error identifier. IPC comprises CMP, FWD, LOC and SUB.The forward displacement of an error is the non-inclusive number ofbytes between the first data byte of the sector and the byte in error.

CMP is a comparator circuit (block 234) with inputs FWD₋₋ OUT and LOC₋₋OUT and outputs FWD₋₋ LT0, FWD₋₋ LTNI, LOC₋₋ EQ16, LOC₋₋ GT16, LOC₋₋EQ17 and LOC₋₋ GT17, where

FWD₋₋ LT0=(FWD₋₋ OUT<NUM₋₋ ILVS)

FWD₋₋ LTNI=(FWD₋₋ OUT<2*NUM₋₋ ILVS)

LOC₋₋ EQ16=(LOC₋₋ OUT==16)

LOC₋₋ GT16=(LOC₋₋ OUT>16)

LOC₋₋ EQ17=(LOC₋₋ OUT==17)

LOC₋₋ GT17=(LOC₋₋ OUT>17)

FWD is an eleven-bit register (block 231) which holds the forwarddisplacements of errors. Bits 6-0 of FWD can be loaded from RAM₋₋ OUT;when bits 6-0 are so loaded, bits 10-7 of FWD IN are forced to 1001 ifSIZE is one or forced to 0100 if SIZE is zero. For each interleave i inerror (where 0≦i<NUM₋₋ ILVS), FWD is initialized to NUM₋₋ BYTS+i beforethe search for roots is begun. Each time the FDC is clocked, FWD isloaded from SUB₋₋ OUT. If FDO₋₋ OUT is zero before the FDC is clocked,then after the FDC is clocked, FWD holds the forward displacement of theerror just located.

LOC is a five-bit counter (block 233) which holds the number of timesthe FDC has been clocked, up to eighteen. LOC can be cleared to zero. IfLOC₋₋ GT17 is zero when the FDC is clocked, LOC is incremented.

SUB is an eleven-bit minus four-bit unsigned subtraction circuit (block232) implementing

    SUB.sub.-- OUT=FWD.sub.-- OUT-NUM.sub.-- ILVS.

NUM-ILVS is determined by the SIZE signal as described herein.

RAM is a 226-by-eight-bit random-access memory which holds thetime-domain CRC residue and ECC remainder bytes, frequency-domain ECCsyndromes, polynomial coefficients and other data used by the erroridentifier. Usage of RAM is as shown in TABLE I. On power up or otherinitialization, the external microcontroller must write desired errorthreshold values to locations ILV₋₋ THR and SCT₋₋ THR, and must writezero to locations SIG₋₋ K+9 through SIG₋₋ K+16 and SIG₋₋ N+9 throughSIG₋₋ N+16.

The error identifier has no need to access individual CRC residue or ECCremainder bytes using immediate addresses. In the preferred embodimentof the invention, implementation cost is reduced by storing these bytesbeginning at RES₋₋ REM equal to 3Eh, above all other variables stored inthe RAM, so that all immediate addresses used to access other variablesneed be only six bits wide. At the beginning of the error identificationprocedure, the four CRC residue bytes must be fetched from the RAM inreverse order and stored in the CRA registers and six bytes in the RAMmust be cleared to zero. These six bytes are the four locations used foraccumulating the adjusted CRC residue beginning at ADJ₋₋ CRC, thelocation used for the total error count (TOT₋₋ ERR), and the locationused for the maximum interleave error count (MAX₋₋ ERR). It isadvantageous to place ADJ₋₋ CRC at 3Ah, TOT₋₋ ERR at 39h and MAX-ERR at38h, so that the address register used to access the four CRC residuebytes at consecutive decreasing addresses need not be reloaded beforebeginning a loop which clears the next six bytes at consecutivedecreasing addresses. By placing SIG₋₋ K at 06h and SIG₋₋ N at 17h, theregisters implemented for SK and SN need be only five bits wide, andthis leaves room at 28h for storing the syndromes. The interleave errorthreshold (ILV₋₋ THR) and sector error threshold (SCT₋₋ THR) are placedadjacent to each other at the beginning of the RAM at 00h and 01h,respectively, to simplify microcontroller access. The remainingvariables including the number of interleaves left to be processed(ILV₋₋ LFT), the address or R₁₅ of the interleave being processed (R15₋₋ADR), the seven least-significant bits of the initial forwarddisplacement value for the interleave being processed (MAX₋₋ FWD) andcounter n of the iterative algorithm (N) are placed at the remaining RAMlocations 02h, 03h, 04h and 05h respectively.

                  TABLE I                                                         ______________________________________                                        Address Map of the Error Identifier RAM                                       LABEL     DECIMAL ADDRESS HEX ADDRESS                                         ______________________________________                                        ILV.sub.-- THR                                                                          0               01                                                  SCT.sub.-- THR                                                                          1               01                                                  ILV.sub.-- LFT                                                                          2               02                                                  R15.sub.-- ADR                                                                          3               03                                                  MAX.sub.-- FWD                                                                          4               04                                                  N         5               05                                                  SIG.sub.-- K                                                                            6               06                                                  SIG.sub.-- N                                                                            23              17                                                  S         40              28                                                  MAX.sub.-- ERR                                                                          56              38                                                  TOT.sub.-- ERR                                                                          57              39                                                  ADJ.sub.-- CRC                                                                          58              3A                                                  RES.sub.-- REM                                                                          62              3E                                                  ______________________________________                                    

ROM is a 157-by-seventeen-bit read-only memory which contains thesequence of instructions required to identify errors. TABLE II shows thecontents of ROM in binary and hexadecimal form.

                                      TABLE II                                    __________________________________________________________________________    Contents of the Error Identifier ROM                                          ADDR                                                                              LQPRDSTFC76543210                                                                         HEX  ADDR                                                                              LQPRDSTFC76543210                                                                         HEX                                      __________________________________________________________________________    00h 00000000000000000                                                                         00000                                                                              28h 01110010100100000                                                                         0E520                                    01h 00101100001000001                                                                         05841                                                                              29h 00110100010000010                                                                         06882                                    02h 01100011100000100                                                                         0C704                                                                              2Ah 11101011000110010                                                                         1D632                                    03h 10101000001000010                                                                         15042                                                                              2Bh 00100101110000101                                                                         04B85                                    04h 11110110000000110                                                                         1EC06                                                                              2Ch 11100011000101111                                                                         1C62F                                    05h 01100010100000110                                                                         0C506                                                                              2Dh 00100001110000100                                                                         04384                                    06h 11110010000000000                                                                         1E400                                                                              2Eh 00100000000000011                                                                         04003                                    07h 01110010000000000                                                                         0E400                                                                              2Fh 01100000000110001                                                                         0C031                                    08h 11101000000010000                                                                         1D010                                                                              30h 10000000000000000                                                                         10000                                    09h 01110000100000011                                                                         0E103                                                                              31h 11110110001011110                                                                         1EC5E                                    0Ah 11101001000001101                                                                         1D20D                                                                              32h 00101100000000110                                                                         05806                                    0Bh 00101000001100010                                                                         05062                                                                              33h 01100111100110101                                                                         0CF35                                    0Ch 00101000001011000                                                                         05058                                                                              34h 11110000100001110                                                                         1E10E                                    0Dh 01110000100000100                                                                         0E104                                                                              35h 11110010000100000                                                                         1E420                                    0Eh 11100000000010011                                                                         1C013                                                                              36h 00101100000010111                                                                         05817                                    0Fh 00101000000000101                                                                         05005                                                                              37h 01100111100111001                                                                         OCF39                                    10h 00101000000110000                                                                         05030                                                                              38h 11110000100011111                                                                         1E11F                                    11h 01110000100000100                                                                         0E104                                                                              39h 11110010000100000                                                                         1E420                                    12h 00101000000001010                                                                         0500A                                                                              3Ah 00101100111111010                                                                         059FA                                    13h 01110000100000010                                                                         0E102                                                                              3Bh 01110000100000101                                                                         0E105                                    14h 01111000100110100                                                                         0F134                                                                              3Ch 00101101000101110                                                                         05A2E                                    15h 01110100000000011                                                                         0E803                                                                              3Dh 01100000000111110                                                                         0C03E                                    16h 00101100000000111                                                                         05807                                                                              3Eh 10110100001100000                                                                         16860                                    17h 01100011100011000                                                                         0C718                                                                              3Fh 01011101100000000                                                                         0BB00                                    18h 11011000001000000                                                                         1B040                                                                              40h 11100100001001010                                                                         1C84A                                    19h 01011000001000000                                                                         0B040                                                                              41h 00101011110000000                                                                         05780                                    1Ah 00101100000101000                                                                         05828                                                                              42h 11101011001000101                                                                         1D645                                    1Bh 01100111100011100                                                                         0CF1C                                                                              43h 00101000000000001                                                                         05001                                    1Ch 11110011100100000                                                                         1E720                                                                              44h 01000010001000000                                                                         08440                                    1Dh 01110011100100000                                                                         0E720                                                                              45h 00011000000000000                                                                         03000                                    1Eh 01111000000000101                                                                         0F005                                                                              46h 01100000001000111                                                                         0C047                                    1Fh 00101100000000111                                                                         05807                                                                              47h 01011010001000000                                                                         0B440                                    20h 01100011100100001                                                                         0C721                                                                              48h 11011001100100000                                                                         1B320                                    21h 11011000001000000                                                                         1BO40                                                                              49h 01110010101100000                                                                         0E560                                    22h 01011000001000000                                                                         0B040                                                                              4Ah 00111010110000101                                                                         07585                                    23h 11101010010000010                                                                         1D482                                                                              4Bh 11101011000111011                                                                         1D63B                                    24h 00101100000101000                                                                         05828                                                                              4Ch 00111100100000101                                                                         07905                                    25h 00100100000000001                                                                         04801                                                                              4Dh 01111000110011100                                                                         1F19C                                    26h 01101111100100111                                                                         0DF27                                                                              4Eh 01110100100000100                                                                         0E904                                    27h 11001101111100000                                                                         19BE0                                                                              4Fh 00101110000000000                                                                         05C00                                    50h 00111010000111001                                                                         07439                                                                              78h 01100000001111010                                                                         0C07A                                    51h 01100000001010011                                                                         0C053                                                                              79h 10010000100000000                                                                         12100                                    52h 11110000100111001                                                                         1E139                                                                              7Ah 11110110001011110                                                                         1EC5E                                    53h 10111000001100000                                                                         17060                                                                              7Bh 11101111001011011                                                                         1DE5B                                    54h 00100010001111111                                                                         0447F                                                                              7Ch 00110100000000101                                                                         06805                                    55h 00110110110111000                                                                         06DB8                                                                              7Dh 11101100010010111                                                                         1D897                                    56h 11100011001011001                                                                         1C659                                                                              7Eh 00101100000111010                                                                         0583A                                    57h 00101010000000001                                                                         05401                                                                              7Fh 01100011110000000                                                                         0C780                                    58h 0l110000100111000                                                                         0E138                                                                              80h 11001011110010110                                                                         19796                                    59h 01110000100000101                                                                         0E105                                                                              81h 01110010100100000                                                                         0E520                                    5Ah 00010001000000000                                                                         02200                                                                              82h 00111000100000100                                                                         07104                                    5Bh 01100000001011101                                                                         0C05D                                                                              83h 01110000100000100                                                                         0E104                                    5Ch 11110111001011000                                                                         1EE58                                                                              84h 00111000100000011                                                                         07103                                    5Dh 11110111001011100                                                                         1EE5C                                                                              85h 01110000100000011                                                                         0E103                                    5Eh 11101101001110001                                                                         1DA71                                                                              86h 00111000010000010                                                                         07082                                    5Fh 00101110000101000                                                                         05C28                                                                              87h 11100011000010100                                                                         1C614                                    60h 001l1000010000101                                                                         07085                                                                              88h 01110000100000010                                                                         0E102                                    61h 01l10000100000101                                                                         0E105                                                                              89h 00111000000111000                                                                         07038                                    62h 01000001001000000                                                                         08240                                                                              8Ah 11101011010011010                                                                         1D69A                                    63h 01100000001100100                                                                         0C064                                                                              8Bh 00101100000111010                                                                         0583A                                    64h 01110000100110111                                                                         0E137                                                                              8Ch 01100011110001101                                                                         0C78D                                    65h 01000010010000000                                                                         08480                                                                              8Dh 10110100001000000                                                                         16840                                    66h 01000010100000000                                                                         08500                                                                              8Eh 11101100010011011                                                                         1D89B                                    67h 10111000000110111                                                                         17037                                                                              8Fh 00110100000000000                                                                         06800                                    68h 0101l010100000000                                                                         0B500                                                                              90h 00110101110111000                                                                         06BB8                                    69h 01001000001000000                                                                         09040                                                                              91h 11100011010011100                                                                         1C69C                                    6Ah 01100110101101011                                                                         0CD6B                                                                              92h 00110100000000001                                                                         06801                                    6Bh 11000101000100000                                                                         18A20                                                                              93h 00110101110111001                                                                         06BB9                                    6Ch 01001001001000000                                                                         09240                                                                              94h 11100011010011100                                                                         1C69C                                    6Dh 11100100010010111                                                                         1C897                                                                              95h 00000000000000000                                                                         00000                                    6Eh 00010010000000000                                                                         02400                                                                              96h 00010100000000000                                                                         02800                                    6Fh 11101101001101111                                                                         1DA6F                                                                              97h 00101000001000000                                                                         05040                                    70h 00000000000000001                                                                         00001                                                                              98h 11101011010000010                                                                         1D682                                    71h 11101110001111011                                                                         1DC7B                                                                              99h 01110000100111000                                                                         0E138                                    72h 01110110101011100                                                                         0ED5C                                                                              9Ah 00010100000000100                                                                         02804                                    73h 00110100000000010                                                                         06802                                                                              9Bh 00010100000000010                                                                         02802                                    74h 00100101110000101                                                                         04B85                                                                              9Ch 00010100000000001                                                                         02801                                    75h 11101011001111011                                                                         1D67B                                                         76h 00000000000000000                                                                         00000                                                         77h 00100001001111111                                                                         0427F.                                                        __________________________________________________________________________

ERROR IDENTIFIER MICROENGINE INSTRUCTION SET

Each instruction comprises seventeen bits. The instruction bits arelabeled as follows:

    __________________________________________________________________________    Bit:                                                                              16                                                                              15                                                                              14                                                                              13                                                                              12                                                                              11                                                                              10                                                                              9 8 7 6 5 4 3 2 1 0                                         Label:                                                                            L Q P R D S T F C 7 6 5 4 3 2 1 0                                         __________________________________________________________________________

The Opcode of an instruction comprises bits Q, P and R. `x` represents abit whose value may be either one or zero. `a` represents a bit which ispart of an immediate ROM or RAM address; it may be either one or zero.`v` represents a bit which is part of an immediate value; it may beeither one or zero.

Conventions used for immediate values, immediate addresses and indirectaddresses are as follows:

    ______________________________________                                        VAL7    Use the eight-bit value in bits 7-0 of IR.sub.-- OUT after                    replacing the value of bit 7 with that of bit 6. This                         is equivalent to treating bits 6-0 of IR.sub.-- OUT as a                      signed seven-bit integer with value in the range -64                          to +63.                                                               *(ADR6) Read or write RAM at the address specified by bits                            5-0 of IR.sub.-- OUT.                                                 *(A0)   Read or write RAM at the address specified by                                 A0.sub.-- OUT.                                                        *(A0++) Read or write RAM at the address specified by                                 A0.sub.-- OUT, then increment the A0 register.                        *(A1++) Read or write RAM at the address specified by                                 A1.sub.-- OUT,then increment the A1 register.                         *(A1--) Read or write RAM at the address specified by                                 A1.sub.-- OUT, then decrement the A1 register.                        ______________________________________                                    

When any instruction with bit L equal to one (except a Conditional₋₋Branch or Search₋₋ For₋₋ Root instruction) is executed, LC₋₋ OUT isexamined. If LC₋₋ OUT is zero, IA is incremented; otherwise, LC isdecremented and IA is loaded from LA₋₋ OUT.

When a Search₋₋ For₋₋ Root instruction with bit L equal to one isexecuted, FDC₋₋ OUT, FWD₋₋ OUT and LOC₋₋ OUT are examined. If FDC₋₋ OUTis zero, FWD₋₋ LTNI is one, or LOC₋₋ EQ16 is one, IA is incremented andbits L, Q, P and R of IR₋₋ IN are forced to zero to prevent execution ofthe next instruction by transforming it into a NOP instruction;otherwise, IA is loaded from LA₋₋ OUT.

    ______________________________________                                        OPCODE 000: NOP INSTRUCTIONS                                                  LQPR  DSTFC    76543210                                                       ______________________________________                                        x000  xxxxx    xxxxxxx0 No Operation.                                         x000  xxxxx    xxxxxxx1 No Operation except when this                                                 instruction immediately follows a                                             Conditional.sub.-- Branch instruction                                         If VREADY is zero when the                                                    Conditional.sub.-- Branch instruction is                                      executed, this instruction forces bit                                         D of IR.sub.-- OUT to zero.                           OPCODE 001: MISCELLANEOUS INSTRUCTIONS                                        LQPR  DSTFC    76543210                                                       ______________________________________                                        x001  xxxx1    xxxxxxxx Load LN from LK.sub.-- OUT.                           x001  xxx1x    xxxxxxxx Load LK from LN.sub.-- OUT.                           x001  xx1xx    xxxxxxxx Correct.sub.-- Error: If allowed by the                                       current configuration signials and                                            FWD.sub.-- OUT, assert the signal                                             which initiates an error correction                                           vector transfer. FWD.sub.-- OUT and                                           DL.sub.-- OUT are the forward                                                 displacement and value of the                                                 error, respectively.                                  x001  x1xxx    xxxxxvvv Stop: Assert the error signal speci-                                          fied by one of bits 2-0 equal to one                                          (if any) and stop the error                                                   identifier.                                                         Bit Error signal                                                              2   ECC.sub.-- ERR                                                            1   CRC.sub.-- ERR                                                            0   THR.sub.-- ERR                                              x001  1xxxx    xxxxxxxx Load A0 from SN.sub.-- OUT and load                                           A1 from SK.sub.-- OUT.                                OPCODE 110: BRANCH-CONTROL INSTRUCTIONS                                       Initiate.sub.-- DO.sub.-- Loop:                                               LQPR  DSTFC    76543210                                                       ______________________________________                                        0110  xxxx0    aaaaaaaa Load LA from bits 7-0 of IR.sub.-- OUT                                        and load LC from LN.sub.-- OUT.                       0110  vvvv1    aaaaaaaa Load LA from bits 7-0 of IR.sub.-- OUT                                        and load LC from bits D, S, T, F.                     Conditional.sub.-- Branch:                                                    LQPR  DSTFC    76543210                                                       ______________________________________                                        1110  xvvvx    aaaaaaaa If the state of the signal selected by                                        bits S, T and F of IR.sub.-- OUT does                                         not match bit D, load IA from bits                                            7-0 of IR.sub.-- OUT.                                               STF  CONDITION                                                                000  NOT (SIZE)                                                               001  NOT (FORM)                                                               010  NZR.sub.-- OUT                                                           011  GTZ.sub.-- OUT                                                           100  ZRO.sub.-- OUT                                                           101  FZD.sub.-- OUT                                                           110  LOC.sub.-- EQ17                                                          111  FWD.sub.-- LT0                                             ______________________________________                                    

OPCODE 01x: ADD INSTRUCTIONS

Perform an eight-bit addition operation with carry-in:

    ADD.sub.-- OUT=M1.sub.-- OUT+M2.sub.-- OUT+CARRY.

Mi₋₋ OUT is specified by bits T and F of the instruction. If bit 7 ofthe instruction is one, each bit of M1₋₋ OUT is inverted. M2₋₋ OUT isspecified by bits R, 6 and 5 of the instruction. CARRY is bit C of theinstruction. ADD₋₋ OUT is stored in the destination (s) specified bybits D and S of the instruction. The operation

    ADD.sub.-- OUT=M2.sub.-- OUT-M1.sub.-- OUT

is selected by bits 7 and C of the instruction both equal to one. Theoperation

    ADD.sub.-- OUT=M2.sub.-- OUT+1,

is selected by bits T, F and 7 of the instruction all equal to zero andbit C of the instruction equal to one. The operation

    ADD.sub.-- OUT=M2.sub.-- OUT-1,

is selected by bits T, F and C of the instruction all equal to zero andbit 7 of the instruction equal to one.

    __________________________________________________________________________    TF7                                                                              M1.sub.-- OUT                                                                          R65                                                                              M2.sub.-- OUT                                                                       DS DESTINATION(S)                                        __________________________________________________________________________    000                                                                              0        0vv                                                                              VAL7  00 LN                                                    010                                                                              D0.sub.-- OUT                                                                          10a                                                                              *(ADR6)                                                                             01 D0                                                    1x0                                                                              LN.sub.-- OUT                                                                          110                                                                              *(A1++)                                                                             10 D1                                                    001                                                                              FFh      111                                                                              *(A0++)                                                                             11 D0=D1=ADD.sub.-- OUT                                  011                                                                              D0.sub.-- OUT ⊕ FFh                                                    1x1                                                                              LN.sub.-- OUT ⊕ FFh                                                    __________________________________________________________________________

The following combinations are exceptions to the foregoing or causeadditional functions to be performed:

    ______________________________________                                        LQPR  DSTFC7   6543210                                                        ______________________________________                                        x01x  xx11xx   xxxxxxx  Disregard bits R, 6 and 5; instead,                                           use LK.sub.-- OUT as M2.sub.-- OUT.                   x01x  110x00   xxxxxxx  In addition to the normal function,                                           store ADD.sub.-- OUT in A1.                           x011  100000   11xxxxx  Load.sub.-- FDC.sub.-- Sig: In addition to the                                normal function, store ADD.sub.-- OUT                                         in the FDC register D(i) specified                                            by i=A1.sub.-- OUT and decrement A1.                  X010  110011   vvvvvvv  Setup.sub.-- Iteralgo: In addition to the                                     normal function, store the initial                                            value of D0.sub.-- OUT in DK, clear                                           LN and LK to zero, preset SN to                                               0Eh, and preset SK to 1Fh.                            X010  111000   vvvvvvv  Setup.sub.-- A0.sub.-- A1.sub.-- D0.sub.-- D1:                                In                                                                            addition to the normal function,                                              store ADD.sub.-- OUT in A1, clear D0                                          and D1 to zero, and load A0 from                                              SN.sub.-- OUT.                                        X010  110100   vvvvvvv  Setup.sub.-- Compute.sub.-- Dn: In addition to                                the normal function,, store                                                   ADD.sub.-- OUT in A1, clear D0 and                                            D1 to zero, load A0 from                                                      SN.sub.-- OUT, decrement SK, and                                              increment LK.                                         ______________________________________                                    

OPCODE 10x: VMS INSTRUCTIONS

Perform a finite-field variable multiply-and-sum operation:

    VMS.sub.-- OUT=(M1.sub.-- OUT*M2.sub.-- OUT)⊕M3.sub.-- OUT.

MI₋₋ OUT is specified by bits T and F of the instruction. M2₋₋ OUT isspecified by bits R, 6 and 5 of the instruction. M3₋₋ OUT is specifiedby bits C and 7 of the instruction. VMS₋₋ OUT is stored in thedestination(s) specified by bits D and S of the instruction. Note thatwhen bits D and S of the instruction are both zero, the initial value ofDO₋₋ OUT is stored in DK. If bits T and F are both one, the CRA isclocked.

    __________________________________________________________________________    TF M1.sub.-- OUT                                                                        R65                                                                              M2.sub.-- OUT                                                                        C7 M3.sub.-- OUT                                                                       DS DESTINATION(S)                                __________________________________________________________________________    00 A135L.sub.-- OUT                                                                     000                                                                              AL.sub.-- OUT                                                                        00 0     01 D0                                            01 D0.sub.-- OUT                                                                        001                                                                              D0.sub.-- OUT                                                                        10 D1.sub.-- OUT                                                                       10 D1                                            10 DK.sub.-- OUT                                                                        010                                                                              DL.sub.-- OUT                                                                        01 *(A0++)                                                                             11 D0=D1=VMS.sub.-- OUT                          11 CRA.sub.-- OUT                                                                       011                                                                              FDC.sub.-- OUT                                                                       11 *(A1) 00 DK=D0.sub.-- OUT,                                       100                                                                              *(A1--)            D0=D1=VMS.sub.-- OUT                                    101                                                                              *(A1++)                                                                    110                                                                              *(A0)                                                                      111                                                                              *(A0++)                                                          __________________________________________________________________________

The following combinations are exceptions to the foregoing or causeadditional functions to be performed:

    ______________________________________                                        LQPR  DSTFC7   6543210                                                        ______________________________________                                        x101  100000   10xxxxx  Load.sub.-- FDC.sub.-- Rem: In addition to                                    the normal function, store                                                    VMS.sub.-- OUT in the FDC register                                            D(i) specified by i=A1.sub.-- OUT,                                            decrement A1, add NUM.sub.-- ILVS to                                          A0, store A135.sub.-- OUT in A135, and                                        if M40.sub.-- OUT is one, set NZR.                    X100  110111   11xxxxx  Compute-Syndrome: Disregard bits                                              D and S. Instead, store VMS.sub.-- OUT                                        in D1. In addition, clock the FDC                                             and store A247.sub.-- OUT in D0.                      x100  001000   10xxxxx  Swap.sub.-- K.sub.-- N.sub.-- Regs: In addition                               to                                                                            the normal function, exchange the                                             contents of SN and SK and ex-                                                 change the contents of LN and LK.                     ______________________________________                                    

OPCODE 111: ASSIGNMENT INSTRUCTIONS

If bit F of any instruction with Opcode 111 is one, the FDC is clocked.If both bits S and T of any instruction with Opcode 111 are one, the CRAis clocked.

    __________________________________________________________________________    LQPR                                                                              DSTFC7                                                                             6543210                                                              __________________________________________________________________________    x111                                                                              000xx0                                                                             0aaaaaa                                                                            Write RAM at the address in bits 5-0 from the                                 source specified by bits F and C of IR.sub.-- OUT.                            FC  SOURCE   DESTINATION                                                      00  0        *(ADR6)                                                          01  DL.sub.-- OUT                                                             1x  FDC.sub.-- OUT                                              x111                                                                              001xx0                                                                             xxxxxxx                                                                            Write RAM at the address specified by bits 6                                  and 5 of IR.sub.-- OUT from the source specified by                           bits F and C of IR.sub.-- OUT.                                                FC SOURCE  65 DESTINATION                                                     00 0       00 *(A1--)                                                         01 D1.sub.-- OUT                                                                         01 *(A1++)                                                         1x FDC.sub.-- OUT                                                                        10 *(A0)                                                                      11 *(A0++)                                           x111                                                                              010xxx                                                                             0aaaaaa                                                                            Load the destination specified by bit C of                                    IR.sub.-- OUT from bits 6-0 of the value read from                            RAM at the address in bits 5-0 of IR.sub. -- OUT.                             SOURCE  C   DESTINATION                                                       *(ADR6) 0   A0                                                                        1   FWD                                                               Note: Bit 7 of A0 is loaded with 0; bits 10-8 of                              FWD are loaded with bits 10-8 of NUM.sub.-- ILVS.               x111                                                                              10000v                                                                             vvvvvvv                                                                            Load.sub.-- A135L: Load A135L with the value in bits                          7-0 of IR.sub.-- OUT.                                           x111                                                                              10001v                                                                             vvvvvvv                                                                            Initialize.sub.-- FDC: Load A135L with the value in                           bits 7-0 of IR.sub.-- OUT, preset AL to α.sup.-1,                       clear                                                                         each FDC register D(i) to zero, and clear LOC                                 and NZR to zero.                                                x111                                                                              011100                                                                             10vvvvx                                                                            Search.sub.-- For.sub.-- Root (described above).                __________________________________________________________________________

The sequence of instructions used in the preferred embodiment toimplement the error identification procedure is shown in TABLE III. Thissequence is implemented in the contents of ROM shown in TABLE II. Avariable stored in RAM at a label shown in TABLE I is denoted by theparenthesized label preceded by "*"; the value of a label is denoted bythe label itself.

                                      TABLE III                                   __________________________________________________________________________    Error Identifier Instruction Sequence                                         __________________________________________________________________________    00h                                                                              No.sub.-- Operation(0);                                                    01h                                                                              D0 = D1 = A1 = ADD(0, RES.sub.-- REM+3);                                   02h                                                                              Initiate.sub.-- D0.sub.-- Loop(3, 04h);                                    03h                                                                              D1 = ADD(0, RES.sub.-- REM+4);                                             04h                                                                               Clock.sub.-- CRA(*(A1--),0,06h);                                          05h                                                                              Initiate.sub.-- DO.sub.-- Loop(2, 06h);                                    06h                                                                               *(A1--) = 0;                                                              07h                                                                               *(A1--) = 0;                                                              08h                                                                              IF(!SIZE != 1, 10h);                                                       09h                                                                              *(R15.sub.-- ADR) = D1;                                                    0Ah                                                                               IF(!FORM != 1, 0Dh);                                                      0Bh                                                                               D1 = ADD(0, 610 & 7Fh);                                                   0Ch                                                                               D1 = ADD(0, 600 & 7Fh);                                                   0Dh                                                                               *(MAX.sub.-- FWD) = D1;                                                   0Eh                                                                               IF(!SIZE != 0, 13h);                                                      0Fh                                                                               D1 = ADD(0, 5);                                                           10h                                                                              D1 = ADD(0, 1200 & 7Fh);                                                   11h                                                                              *(MAX.sub.-- FWD) = D1;                                                    12h                                                                              D1 = ADD(0, 10);                                                           13h                                                                              *(ILV.sub.-- LFT) = D1;                                                    14h                                                                              Initialize.sub.-- FDC(α.sup.15);                                     15h                                                                              A0 = *(R15.sub.-- ADR) & 7fh;                                              16h                                                                              D0 = D1 = A1 = ADD(0, 7);                                                  17h                                                                              Initiate.sub.-- O0.sub.-- Loop(3, 18h);                                    18h                                                                               Load.sub.-- FDC.sub.-- Rem() ;                                            19h                                                                               Load.sub.-- FDC.sub.-- Rem();                                             1Ah                                                                              D0 = D1 = A1 = ADD(0, S);                                                  1Bh                                                                              Initiate.sub.-- DO.sub.-- Loop(7, 1Ch);                                    1Ch                                                                               *(A1++) = FDC.sub.-- OUT, Clock.sub.-- FDC();                             1Dh                                                                               *(A1++) = VRC.sub.-- OUT, Clock.sub.-- FDC();                             1Eh                                                                              Load.sub.-- A135L(α.sup.75);                                         1Fh                                                                              D0 = D1 = A1 = ADD(0, 7);                                                  20h                                                                              Initiate.sub.-- DO.sub.-- Loop(3, 21h);                                    21h                                                                               Load.sub.-- FDC.sub.-- Rem();                                             22h                                                                               Load.sub.-- FDC.sub.-- Rem();                                             23h                                                                              IF(NZR.sub.-- OUT != 1, 84h);                                              24h                                                                              D0 = D1 = A1 = ADD(0, S);                                                  25h                                                                              D0 = ADD(0, 1);                                                            26h                                                                              Initiate.sub.-- DO.sub.-- Loop(15, 27h);                                   27h                                                                               Compute.sub.-- Syndrome();                                                28h                                                                               *(A1++) = D1;                                                             29h                                                                              D0 = ADD(-1, *(ILV.sub.-- LFT));                                           2Ah                                                                              IF(GTZ.sub.-- OUT != 1, 31h);                                              2Bh                                                                              D0 = ADD(-D0.sub.-- OUT, 5);                                               2Ch                                                                               IF(GTZ.sub.-- OUT != 0,2Fh);                                              2Dh                                                                               LN = ADD(-D0.sub.-- OUT, 4);                                              2Eh                                                                               LN = ADD(0, 3);                                                           2Fh                                                                               Initiate.sub.-- D0.sub.-- Loop(LN.sub.-- OUT, 31h);                       30h                                                                               No.sub.-- operation(0)                                                    31h                                                                               Clock CRA(*(A0), 0,1Eh),                                                  32h                                                                              D0 = D1 = A1 = ADD(0, SIG.sub.-- K);                                       33h                                                                              Initiate.sub.-- D0.sub.-- Loop(7, 35h);                                    34h                                                                              *(SIG.sub.-- K+8) = D1;                                                    35h                                                                               *(A1++) = 0;                                                              36h                                                                              D0 = D1 = A1 = ADD(0, SIG.sub.-- N);                                       37h                                                                              Initiate.sub.-- D0.sub.-- Loop(7, 39h);                                    38h                                                                              *(SIG.sub.-- N+8) = D1;                                                    39h                                                                               *(A1++) = 0;                                                              3Ah                                                                              Setup.sub.-- Iteralgo(7Ah);                                                3Bh                                                                              *(N) = D1;                                                                 3Ch                                                                              Setup.sub.-- Compute.sub.-- DN();                                          3Dh                                                                              Initiate.sub.-- D0.sub.-- Loop(LN.sub.-- OUT, 3Eh);                        3Eh                                                                               D0 = ADD(0, *(A0++));                                                     3Fh                                                                               D0 = D1 =  VMS(D0.sub.-- OUT, *(A1--), D1.sub.-- OUT);                    40h                                                                              IF(ZRO.sub.-- OUT != 0, 4Ah);                                              41h                                                                              D1 = ADD(-LN.sub.-- OUT, LK.sub.-- OUT);                                   42h                                                                               IF(GTZ.sub.-- OUT != 1, 45h);                                             43h                                                                               D1 = ADD(0, 1);                                                           44h                                                                               Swap.sub.-- K.sub.-- N.sub.-- Regs()                                      45h                                                                               A0 = SN.sub.-- OUT, A1 = SK.sub.-- OUT;                                   46h                                                                               Initiate.sub.-- D0.sub.-- Loop(LN.sub.-- OUT, 47h);                       47h                                                                               D1 = VMS(DK.sub.-- OUT, *(A0), 0);                                        48h                                                                               D1 = VMS(D0.sub.-- OUT, *(A1++), D1.sub.-- OUT);                          49h                                                                               *(A0++) = D1;                                                             4Ah                                                                              D1 = ADD(-LN.sub.-- OUT, *(N));                                            4Bh                                                                              IF(GTZ.sub.-- OUT != 1, 3Bh);                                              4Ch                                                                              D0 = D1 = ADD(+1, *(N));                                                   4Dh                                                                              Initialize.sub.-- FDC(α.sup.120));                                   4Eh                                                                              FWD = (NUM.sub.-- BYTS & 780h) | (*(MAX.sub.-- FWD) & 7Fh);       4Fh                                                                              Setup.sub.-- A0.sub.-- A1.sub.-- D0.sub.-- D1(0);                          50h                                                                              D1 = ADD(LN.sub.-- OUT, *(TOT.sub.-- ERR));                                51h                                                                              Initiate.sub.-- DO.sub.-- Loop(LN.sub.-- OUT, 53h);                        52h                                                                              *(T0T.sub.-- ERR) = D1;                                                    53h                                                                               Load.sub.-- FDC.sub.-- Sig();                                             54h                                                                              LN = ADD(LN.sub.-- OUT, 7Fh);                                              55h                                                                              D0 = ADD(-LN.sub.-- OUT, *(MAX.sub.-- ERR));                               56h                                                                              IF(GTZ.sub.-- OUT != 0, 59h);                                              57h                                                                              D1 = ADD(LN.sub.-- OUT, 1);                                                58h                                                                               *(MAX.sub.-- ERR) = D1;                                                   59h                                                                              *(N) = D1;                                                                 5Ah                                                                              LK = LN.sub.-- OUT;                                                        5Bh                                                                              Initiate.sub.-- DO.sub.-- Loop(LN.sub.-- OUT, 5Dh);                        5Ch                                                                              Search.sub.-- For.sub.-- Root(18h)                                         5Dh                                                                               Search.sub.-- For.sub.-- Root(1Ch)                                        5Eh                                                                              IF(FZD.sub.-- OUT != 1, 71h);                                              5Fh                                                                              Setup.sub.-- A0.sub.-- A1.sub.-- D0.sub.-- D1(S)                           60h                                                                               D1 = ADD(-1, *(N));                                                       61h                                                                               *(N) = D1;                                                                61h                                                                               DK = D0.sub.-- OUT, D0 = D1 = VMS(D0.sub.-- OUT, D1.sub.-- OUT, 0);       63h                                                                               Initiate.sub.-- D0.sub.-- Loop(LN.sub.-- OUT, 64h);                       64h                                                                               *(S+15) = D1;                                                             65h                                                                               D0 = D1 = VMS(DK.sub.-- OUT,AL.sub.-- OUT,*(A0++)), DK=Initial               D0.sub.-- OUT;                                                             66h                                                                               D0 = D1 = VMS(DK.sub.-- OUT,AL.sub.-- OUT,D1.sub.-- OUT), DK= Initial        D0.sub.-- OUT;                                                             67h                                                                               D1 = ADD(0, *(S+15));                                                     68h                                                                               D1 = VMS(DK.sub.-- OUT, *(A1--), D1.sub.-- OUT);                          69h                                                                               D1 = VMS(A135L.sub.-- OUT, D1.sub.-- OUT, 0).                             6Ah                                                                               Initiate.sub.-- D0.sub.-- Loop(6, 6Bh);                                   6Bh                                                                               D0 = VMS(D0.sub.-- OUT, D0.sub.-- OUT, 0);                                6Ch                                                                               D1 = VMS(D0.sub.-- OUT, D1.sub.-- OUT, 0);                                6Dh                                                                               IF(ZRO.sub.-- OUT != 0, 97h).                                             6Eh                                                                               Correct Errors;                                                           6Fh                                                                               IF(FZD.sub.-- OUT != 1), 6Fh);                                            70h                                                                               No Operation(1);                                                          71h                                                                               IF(LOC.sub.-- EQ17 != 1, 7Bh);                                            72h                                                                               Clock.sub.-- CRA(*(A0),D1.sub.-- OUT,1Ch);                                73h                                                                               D0 = ADD(0, *(ILV.sub.-- LFT));                                           74h                                                                               D0 = ADD(-D0.sub.-- OUT, 5);                                              75h                                                                               IF(GTZ.sub.-- OUT != 1, 7Bh);                                             76h                                                                               No.sub.-- Operation(0);                                                   77h                                                                               LN = ADD(D0.sub.-- OUT, 7Fh);                                             78h                                                                               Initiate.sub.-- D0.sub.-- Loop(LN.sub.-- OUT, 7Ah);                       79h                                                                               LN = LK.sub.-- OUT;                                                       7Ah                                                                               Clock.sub.--l CRA(*(A0),0,1Eh);                                           7Bh                                                                               IF(FWD.sub.-- LTNI != 1, 5Bh);                                            7Ch                                                                               D0 = ADD(0, N);                                                           7Dh                                                                               IF(ZRO.sub.-- OUT != 1, 97h);                                             7Eh                                                                               D0 = D1 = A1 = ADD(0, CRC);                                               7Fh                                                                               Initiate.sub.-- D0.sub.-- Loop(3, 80h)                                    80h                                                                               D1 = VMS(CRA.sub.-- OUT, AL.sub.-- OUT, *(A1)), Clock.sub.-- CRA(*(A0)       ,0,16h);                                                                   81h                                                                               *(A1++) = D1;                                                             82h                                                                               D1 = ADD(1, *(MAX.sub.-- FWD));                                           83h                                                                               *(MAX.sub.-- FWD) = D1;                                                   84h                                                                               D1 = ADD(1, *(R15.sub.-- ADR));                                           85h                                                                               *(R15.sub.-- ADR) = D1;                                                   86h                                                                               D1 = ADD(-1, *(ILV.sub.-- LFT));                                          87h                                                                               IF(GTZ.sub.-- OUT != 0, 14h);                                             88h                                                                               *(ILV.sub.-- LFT) = D1;                                                   89h                                                                              D1 = ADD(0, *(MAX.sub.-- ERR));                                            8Ah                                                                              IF(GTZ.sub.-- OUT != 1, 9Ah);                                              8Bh                                                                              D0 = D1 = A1 = ADD(0, CRC);                                                8Ch                                                                              Initiate.sub.-- D0.sub.-- Loop(3, 8Dh);                                    8Dh                                                                               D0 = ADD(D, *(A1++));                                                     8Eh                                                                               IF(ZRO.sub.-- OUT != 1, 9Bh);                                             8Fh                                                                              D0 = ADD(0, *(ILV.sub.-- THR));                                            90h                                                                              D0 = ADD(-D0.sub.-- OUT, *(MAX.sub.-- ERR));                               91h                                                                              IF(GTZ.sub.-- OUT != 0, 9Ch);                                              92h                                                                              D0 = ADD(0, *(SCT.sub.-- THR));                                            93h                                                                              D0 = ADD-D0.sub.-- OUT, *(TOT.sub.-- ERR));                                94h                                                                              IF(GTZ.sub.-- OUT != 0, 9Ch);                                              95h                                                                              No.sub.-- Operation(0);                                                    96h                                                                              Stop(0);                                                                   97h                                                                              D1 = ADD(0, 40h);                                                          98h                                                                              IF(GTZ.sub.-- OUT != 1, 82h);                                              99h                                                                              *(MAX.sub.-- ERR) = D1;                                                    9Ah                                                                              Stop(4);                                                                   9Bh                                                                              Stop(2);                                                                   9Ch                                                                              Stop(1);                                                                   __________________________________________________________________________

ERROR IDENTIFICATION ALGORITHM

FIG. 25 illustrates the read-sector process for the typical case whereDISABLE is zero, CONT is zero and BUSY is zero at the leading edge ofCG₋₋ RG; other cases are described above. First, circuitry in theEncode/Decode LFSR block of the CL-SM330 computes CRC and ECC redundancyover user-data and vendor-unique/pointer bytes read from the opticaldisk. While CRC and ECC redundancy bits are read CG₋₋ RG is asserted andCRC residue/ECC remainder bits (which are the EXCLUSIVE-OR sum of thecomputed and read redundancy bits) are presented on RMNDR. T7 isasserted while every eighth such bit is presented. CG₋₋ RG, RMNDR and T7are synchronized with RRCLK. The error identifier deserializes the CRCresidue/ECC remainder bits from RMNDR and stores the CRC residue/ECCremainder bytes in RAM. At the trailing edge of CG₋₋ RG if no non-zerobit was detected on RMNDR while CG₋₋ RG was asserted, then the erroridentifier immediately asserts DONE; otherwise, the error identifierasserts BUSY and begins identifying introduced errors.

FIG. 26 illustrates the major steps of the error identification process.In step 1020, the RAM and the CRA are initialized. Then for eachinterleave, the following process is repeated: In step 1030, computefrequency-domain syndromes from the remainder. If all remaindercoefficients are zero, the control is transferred to step 1080.Otherwise in step 1040, compute coefficients of the error locatorpolynomial from the syndromes, and in step 1050, perform the Chiensearch to locate each errors, adjusting the CRC residue whenever anerror is found.

In step 1060, the RAM elements at MAX₋₋ FWD and R15₋₋ ADR areincremented and the RAM element at ILV₋₋ LFT is decremented. If the RAMelement at ILV₋₋ LFT is not zero, control is transferred to step 1030.Otherwise, in step 1080, if any uncorrectable ECC error was detected,the error identifier asserts ECC₋₋ ERR and stops; if any of the four RAMelements at ADJ₋₋ CRC is non-zero, an uncorrectable CRC error has beendetected and the error identifier asserts CRC₋₋ ERR and stops; if thevalue stored in the RAM element at MAX₋₋ ERR exceeds that stored in theRAM element at ILV₋₋ THR or if the value stored in the RAM element atTOT₋₋ ERR exceeds that stored in the RAM element at SCT₋₋ THR, athreshold error has been detected and the error identifier asserts THR₋₋ERR and stop; otherwise the error identifier stops without asserting anyerror signal. When the error identifier stops, it deasserts BUSY andasserts DONE.

FIG. 27 shows the process of initializing the RAM and the CRA each timea sector containing errors is detected. First the four CRC residue bytesstored in RAM at RES₋₋ REM are loaded into the CRA registers. Then thefour RAM elements at ADJ₋₋ CRA, used for accumulating the adjusted CRCresidue, the RAM element at MAX₋₋ ERR, used for the maximum error countand the RAM element at TOT₋₋ ERR, used for the total error count, arecleared to zero. The RAM element at R15₋₋ ADR, used to record theaddress in RAM of R₁₅ of the current interleave, is initialized to RES₋₋REM+4. The RAM element at MAX₋₋ FWD, used to record the sevenleast-significant bits of the sum of NUM₋₋ ILVS and the forwarddisplacement of the last byte of the current interleave, is initializedto NUM₋₋ BYTS. The RAM element at ILV₋₋ LFT, used to record the numberof interleaves remaining to be processed, is initialized to NUM₋₋ ILVS.

FIG. 28 is a flow chart of the compute frequency-domain syndromesoperation. In step 251, A0, A1, A135L and the FDC are initialized forthe first step. Then in step 252, coefficients R₁₅ through R₈ are readfrom RAM, multiplied by A135L₋₋ OUT and stored in D(7) through D(0). Aseach coefficient specified by A0 is processed, VMS₋₋ OUT is stored inthe FDC register specified by A1, NUM₋₋ ILVS is added to A0, A1 isdecremented and A135₋₋ OUT is stored in A135L and NZR is set if M40₋₋OUT is one; all these functions are performed by the microcengine Load₋₋FDC₋₋ Rem instruction. Then in step 253, the FDC is clocked sixteentimes, with the partial syndrome on FDC₋₋ OUT being stored each time inRAM. Then in step 254, A1, A135L and D0 are initialized for the secondstep. Then in step 255, coefficients R₇ through R₀ are read from RAM,multiplied by A135L₋₋ OUT and stored in D(7) through D(0), with A0, A1,A135L and NZR treated as in the first step, again by using themicroengine Load₋₋ FDC₋₋ Rem instruction. Then in step 256, if none ofR₁₅ through R₀ were non-zero, NZR will be zero and the ECC code detectedno errors in the current interleave, the error identification processfor the current interleave is complete so control is passed to step 1060of FIG. 26. Otherwise, the error identification process for the currentinterleave continues with step 257, in which the FDC is clocked sixteentimes, with the EXCLUSIVE-OR sum of the product of FDC₋₋ OUT and D0₋₋OUT and the corresponding partial syndrome from the first step beingstored in RAM and A247₋₋ OUT being stored in D0. This is performed byexecuting a microengine Compute₋₋ Syndrome instruction in which thenormal function of bits D and S is disregarded and instead, VMS₋₋ OUT isstored in D1 at the same time that the FDC is clocked and A247₋₋ OUT isstored in D0. Then in step 258, zero is clocked into the CRA is clockedas necessary to account for any CRC remainder bytes between the lastnon-ECC remainder byte of the current interleave and the first ECCremainder byte of the sector. Note that this clocking of the CRA couldbe performed later, e.g. just before the loop in FIG. 30 is begun orimmediately after the loop of FIG. 30 is interrupted when the FDC hasbeen clocked d-1 times, but that to do so would increase the requiredROM size and time required to perform the error identificationprocedure.

FIG. 29 is a flow chart of the compute error locator polynomialcoefficients operation. This implements the new iterative algorithm ofFIG. 13, as detailed in TABLE III. In the preferred embodiment of theinvention, the swapping of the contents of LK and LN; DK and D0; and SKand SN are performed using a single microengine Swap₋₋ K₋₋ N₋₋ Regsinstruction after one has been stored into D1 using a microengine ADDinstruction. When the Swap₋₋ K₋₋ N₋₋ Regs instruction is executed, theproduct of D1₋₋ OUT and DK is stored in D0 and D1 at the same time thatD0₋₋ OUT is stored in DK, LK₋₋ OUT is stored in LN, LN₋₋ OUT is storedin LK, SK₋₋ OUT is stored in SN and SN₋₋ OUT is stored in SK.

FIG. 30 is a flow chart of the find errors and adjust CRC operation. Instep 261, A135L, AL, LOC, FWD, A0, A12, D0, D1 and the FDC areinitialized. The RAM element at TOT₋₋ ERR is updated by adding LN. Ifnecessary, the RAM element at MAX₋₋ ERR is updated with LN. The errorlocator polynomial coefficients in RAM at the address contained in SNare loaded into the FDC registers D(i). LN is stored in the RAM locationat N, then LN is decremented. Then in step 262, the FDC is clocked and Lis incremented. Then if none of the conditions for terminating thesearch for roots was met before the FDC was clocked, the loop of step263 is begun, in which zero is clocked into the CRA, the FDC is clockedand L is incremented until one of the terminating conditions is met.When one of the terminating conditions is met, the pipelined nature ofinstruction execution requires that execution of the next instruction beblocked. As disclosed herein, this is accomplished by transforming itinto a No-Operation. Then in step 264, D1 is cleared. Then if condition(a) was met, step 265 is performed. In step 265, the RAM element at N isdecremented and the error value is computed and stored in D1. Computingthe error value requires performing a finite-field variable division.Hardware for performing this operation directly is complex andexpensive. In the preferred embodiment, of the invention, implementationcost is reduced by using the following identity to perform finite-fielddivision as a series of finite-field multiplications: ##EQU17##

Proceeding according to equation (14), finite-field division of x by yis performed by first loading x into D1 and y into D0, then repeatingthe following two-step process b-1 times: store the product of D0₋₋ OUTand D0₋₋ OUT in D0, then store the product of D0₋₋ OUT and D1₋₋ OUT inD1. The value x/y is produced in D1 and if either x or y was zero, D1₋₋OUT is zero.

If the computed error value is zero, an uncorrectable ECC error has beendetected, so this fact is recorded and control is transferred to step1060 of FIG. 26; otherwise, if correction of the identified error isallowed by its forward displacement and the configuration bits, then theforward displacement and value of the identified error are presented tothe CL-SM331 Interface block on FWD₋₋ OUT and D1₋₋ OUT respectively. TheCL-SM331 deasserts VREADY when it is not able to accept an errorcorrection vector. When the error identifier is ready to send an errorcorrection vector, it waits until VREADY is asserted before assertingSEND₋₋ VEC. Then in step 266, D1₋₋ OUT is clocked into the CRA if LOC₋₋GT16 is one. Then if condition (b) was met, step 267 is performed. Instep 267, zero is clocked into the CRA as necessary to account for anyCRC remainder bytes between the last non-CRC remainder byte of thesector and the last non-ECC remainder byte of the current interleave.Then if condition (c) was not met, control is transferred to step 262,otherwise step 268 is performed. In step 268, if the RAM element at N isnot zero, an uncorrectable ECC error has been detected so this fact isrecorded and control is transferred to step 1060 of FIG. 26; otherwise,the EXCLUSIVE-OR sums of the four RAM elements at ADJ₋₋ CRC and theproducts of the contents of the CRA registers and AL₋₋ OUT are stored inRAM at ADJ₋₋ CRC and then control is transferred to step 1060 of FIG.26.

There has been disclosed and described in detail herein the preferredembodiment of the invention and its method of operation. From thedisclosure it will be obvious to those skilled in the art that variouschanges in form and detail may be made to the invention and its methodof operation without departing from the spirit and scope thereof.

We claim:
 1. A circuit for producing a series of electronic values offrequency-domain syndromes of a Reed-Solomon or related code of distanced, the frequency-domain syndromes being denoted S_(m+i) for i from 0 tod-2 wherein m is an offset of a code generator polynomial, from a set ofelectronic values of time-domain remainder coefficients R_(j) for j from0 to d-2 comprising:means of t (d odd) or t+1 (d even) stages forelectronically determining values of said frequency domain syndromes intwo steps, including a step processing electronic values of saidtime-domain remainder coefficients R_(j) for j from 0 to t-1, where t=and producing electronic values of their contributions A_(m+i) to saidfrequency-domain syndromes S_(m+i) according to ##EQU18## and a stepprocessing electronic values of said time-domain remainder coefficientsR_(j) for j from t to d-2 and producing electronic values of theircontributions B_(m+i) to said syndromes S_(m+i) according to ##EQU19##said syndromes S_(m+i) being formed as sums of respective electronicvalues of said contributions A_(m+i) and B_(m+i) for i from 0 to d-2. 2.A circuit for producing a series of electronic values offrequency-domain syndromes of a Reed-Solomon or related code of distanced, the frequency-domain syndromes being denoted S_(m+i) for i from 0 tod-2 wherein m is an offset of a code generator polynomial, a parameterof the code, from a set of electronic values of time-domain remaindercoefficients R_(j) for j from 0 to d-2 comprising: means of t(d odd) ort+1 (d even) stages for electronically determining values of saidfrequency domain syndromes in two steps, including a step processingelectronic values of said time-domain remainder coefficients R_(j) for jfrom 0 to t-1, where t= and producing electronic values of theircontributions A_(m+i) to said syndromes S_(m+i) according to ##EQU20##and a step processing said remainder coefficients R_(j) for j from t tod-2 and computing their contributions B_(m+i) to said frequency-domainsyndromes S_(m+i) according to ##EQU21## said frequency-domain syndromesS_(m+i) being formed as sums of respective electronic values of saidcontributions A_(m+i) and B_(m+i) for i from 0 to d-2.
 3. In a decoderfor an error detection and correction system using a Reed-Solomon codeor related code, a method of electronically decoding a Reed-Solomon codeor related code of distance d having frequency domain syndromes S_(m+i)for i from 0 to d-2, comprising the steps of:(A) receiving an electronicsignal of a code word polynomial; (B) generating electronic values of anerror locator polynomial G (x) from the code word polynomial electronicsignal utilizing two polynomials s.sup.(k) (x) and s.sup.(n) (x) havingrespective coefficients s_(j).sup.(k) and s_(j).sup.(n) for j from 0 tot-1 and using steps of:(a) initializing said coefficient s_(O).sup.(k)to an arbitrary non-zero constant, initializing said coefficients₀.sup.(n) to an arbitrary non-zero constant, initializing a parameterd_(k) to an arbitrary non-zero constant and initializing counters l_(k),l_(n) and n to zero; (b) multiplying said polynomial s.sup.(k) (x) by x,incrementing said counter l_(k) and computing a parameter d_(n)according to ##EQU22## (c) branching to step (g) if said parameter d_(n)is equal to zero; otherwise (d) branching to step (f) if said counterl_(k) is less than or equal to said counter l_(n) ; otherwise (e)interchanging values of said counters l_(k) and l_(n), interchangingvalues of said parameters d_(k) and d_(n), and interchanging thecorresponding coefficients of said polynomials s.sup.(k) (x) ands.sup.(n) (x); (f) computing new coefficients of said polynomials.sup.(n) (x) according to

    σ.sup.(n) (x)=d.sub.k *σ.sup.(n) (x)⊕d.sub.n *σ.sup.(k) (x);

(g) incrementing said counter value n; (h) branching to step (b) if saidcounter n is less than (d-2) or alternatively (t+1_(n)); otherwise (i)assigning s(x)=s.sup.(n) (x) (C) finding root electronic values of theerror locator polynomial and determining corresponding error locations;and (D) correcting said code word polynomial signal or flagging aninformation polynomial as erroneous according to results of step (C). 4.In an electronic system performing identification of introduced errorsin a plurality of interleaved error correction code (ECC) codewords of aReed-Solomon or related code wherein information symbols of the ECCcodewords are protected by a Reed-Solomon Cyclic Redundancy Check (CRC)code of degree dc with a generator polynomial GC(x) and the informationsymbols of the CRC code comprise sums across the ECC codewords ofcorresponding information symbols of the ECC codewords excluding thelast information symbol of the last dc said ECC codewords, these last dcsymbols comprising redundant symbols of the CRC code, a method foradjusting an electronic value of a residue of the CRC code to detectmiscorrections by the ECC, the method comprising steps of:(a) loadingsaid residue of said CRC code into a LFSR which implements a reciprocalpolynomial of said CRC generator polynomial GC(x) and clearing dcaccumulators; (b) before processing each of said ECC codewords in turn,first clocking a zero value into said LFSR a number of times; (c)processing a last information symbol of said ECC codeword, wherein saidprocessing comprises searching for an error in said information symboland clocking a zero value into said LFSR if no error was detected orclocking an error value into said LFSR if an error was detected in saidlast information symbol of said ECC codeword; (d) next clocking a zerovalue into said LFSR a number of times; (e) processing each of remainingsaid information symbols of said ECC codeword in order from next-to-lastto first, wherein said processing comprises searching for an error insaid information symbol and clocking a zero value into said LFSR if noerror was detected or clocking said error value into said LFSR if anerror was detected in said information symbol of said ECC codeword; (f)when all said information symbols of said ECC codeword have beenprocessed, storing a sum of contents of said LFSR and contents ofaccumulators in said accumulators and branching to step (b) if acodeword remains to be processed; otherwise (g) when all saidinformation symbols of all said ECC codewords have been processed,checking that each of said accumulators contains zero values.